1. SPARC Assembler for SunOS 5.x
3. Executable and Linking Format
4. Converting Files to the New Format
B. Examples of Pseudo-Operations
C. Using the Assembler Command Line
D. An Example Language Program
E.2 SPARC-V9 Instruction Set Changes
E.2.1 Extended Instruction Definitions to Support the 64-bit Model
E.2.2 Added Instructions to Support 64 bits
E.2.3 Added Instructions to Support High-Performance System Implementation
E.2.5 Miscellaneous Instruction Changes
E.3 SPARC-V9 Instruction Set Mapping
E.4 SPARC-V9 Floating-Point Instruction Set Mapping
E.5 SPARC-V9 Synthetic Instruction-Set Mapping
E.6 UltraSPARC and VIS Instruction Set Extensions
E.6.5 Graphics Status Register (GSR)
The SPARC-V9 architecture differs from SPARC-V8 architecture in the following areas, expanded below: registers, alternate space access, byte order, and instruction set.
These registers have been deleted:
Table E-1
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These registers have been widened from 32 to 64 bits:
Table E-2
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Note - FSR Floating-Point State Register: fcc1, fcc2, and fcc3 (added floating-point condition code) bits are added and the register widened to 64-bits.
These SPARC-V9 registers are within a SPARC-V8 register field:
Table E-3
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These are registers that have been added.
Table E-4
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Also, there are sixteen additional double-precision floating-point registers, f[32] .. f[62]. These registers overlap (and are aliased with) eight additional quad-precision floating-point registers, f[32] .. f[60]
The SPARC-V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC-V8. This change has no effect on nonprivileged instructions.
Load- and store-alternate instructions to one-half of the alternate spaces can now be included in user code. In SPARC-V9, loads and stores to ASIs 0016 .. 7f16 are privileged; those to ASIs 8016 .. FF16 are nonprivileged. In SPARC-V8, access to alternate address spaces is privileged.
SPARC-V9 supports both little- and big-endian byte orders for data accesses only; instruction accesses are always performed using big-endian byte order. In SPARC-V8, all data and instruction accesses are performed in big-endian byte order.