NAME | SYNOPSIS | FEATURES | DESCRIPTION | RESTRICTIONS | ATTRIBUTES | SEE ALSO
drv/src/pci/dec2115c/dec2115x.h - dec2115c hardware related constants drv/src/pci/dec2115x/dec2115x.c - driver code drv/src/pci/dec2115x/dec2115xprop.h - driver specific properties
DRV
The dec2115x pci-to-pci bridge driver implements:
The common bus driver interface.
The pci bus driver interface
The driver works on an Intel 2115x (21150, 21152, 21153 or 21154) pci-to-pci bus bridge.
The driver uses the pci bus driver interface provided by a parent pci bus driver. Thus, the driver may be applied to any bus driver implementing the pci bus interface.
The dec2115x driver does not provide the drv_probe() routine. In other words, the dec2115x driver does not enumerate the pci bus, nor does it detect a dec2115x device or create an associated device node. When the dec2115x driver is used, associated device nodes should be created either statically by a boot program or dynamically by a separate pci bus enumerator driver.
The dec2115x driver provides the drv_bind() routine. This routine examines the device node properties and thus, identifies a dec2115x compatible device. The routine checks for the pci vendor and device identifiers matching a dec2115x compatible device. If the check is positive, the drv_bind() routine binds the driver to the device node, attaching a PROP_DRIVER property to the device node. The property value specifies the dec2115x driver name. The parent bus driver uses such a property to determine the name of drivers servicing the device. Via the PROP_DRIVER property, the driver gives its name to the parent bus driver, asking it to invoke the drv_int() routine on that device. Note that the drv_bind() routine does nothing if the PROP_DRIVER property is already present in the device node, as the drv_bind() routine will not override existing driver-to-device binding.
The driver provides the drv_unload() entry and supports the driver component unloading. This allows the driver component to be unloaded if it is no longer being used and if it has been dynamically loaded at run time.
The driver supports all bus events specified by the pci bus driver interface. As a consequence, the driver may be used with a hot-pluggable pci bus (for example, CompactPCI).
The Table below summarizes characteristics of the dec2115x pci bus driver.
driver name: | "sun:pci-dec2115x-(bus, pci)" |
---|---|
hardware: | Intel 2115x pci-to-pci bridge |
exported interface: | "bus", "pci" (BUS_CLASS, PCI_CLASS) |
exported interface version: | 0 (PCI_VERSION_INITIAL) |
imported parent interface: | "pci" (PCI_CLASS) |
minimal parent interface version: | 0 (PCI_VERSION_INITIAL) |
device probing (auto-detection): | not supported |
driver-to-device binding | supported (on a node name basis) |
driver unloading: | supported |
system (emergency) shut-down: | supported |
normal device shut-down: | supported |
hot-plug (surprise) device removal: | supported |
The table below lists device node properties used by the dec2115x driver. Note that the column "m/o" specifies whether a given property is mandatory or optional. For optional properties, the column "default value" shows a default value which is used by the driver when a given property is not specified.
Name | Alias | Type | m/o | Default value |
---|---|---|---|---|
"vend-id" | PCI_PROP_VEND_ID | PciPropVendId | m | |
"dev-id" | PCI_PROP_DEV_ID | PciPropDevId | m | |
"dev-num" | PCI_PROP_DEV_NUM | PciPropDevNum | m | |
"func-num" | PCI_PROP_FUNC_NUM | PciPropFuncNum | m | |
"bus-num" | PCI_PROP_BUS_NUM | PciPropBusNum | m | |
"sub-bus-num" | PCI_PROP_SUB_BUS_NUM | PciPropSubBusNum | m | |
"io-regs" | PCI_PROP_IO_REGS | PciPropIoRegs | o | -- |
"mem-rgn" | PCI_PROP_MEM_RGN | Pci64PropMemRgn | o | -- |
"mem-rgn-64" | PCI64_PROP_MEM_RGN | Pci64PropMemRgn | o | -- |
"intr-conf" | D2115X_PROP_INTR_CONF | D2115xPropIntrConf | o | see text below |
"conf" | D2115X_PROP_CONF | D2115xPropConf | o | see text below |
The PCI_PROP_VEND_ID property specifies the dec vendor identifier (must be 0x1011).
The PCI_PROP_DEV_ID property specifies the dec2115x device identifier:
0x0022 for dec21150
0x0024 for dec21152
0x0025 for dec21153
0x0026 for dec21154
The PCI_PROP_DEV_NUM, and PCI_PROP_FUNC_NUM properties specify the configuration space address of the device. This address is the device and function numbers to which the device is connected.
The PCI_PROP_BUS_NUM property specifies the secondary bus number.
The PCI_PROP_SUB_BUS_NUM property specifies the subordinate bus number.
The dec2115x PCI-to-PCI bridge is a transparent bridge. The PCI_PROP_IO_REGS, PCI_PROP_MEM_RGN and PCI64_PROP_MEM_RGN properties configure the transaction forwarding mechanism (between primary and secondary busses) implemented by the dec2115x bridge.
The PCI_PROP_IO_REGS property specifies the programmed and memory-mapped I/O windows assigned for devices residing on the secondary bus. In general, the PCI_PROP_IO_REGS property specifies an array which consists of up to two elements (PciPropIoRegs). One element specifies a window for programmed I/O accesses (PCI_PIO_SPACE) and the other element specifies a window for memory mapped I/O accesses (PCI_MEM_SPACE). If one of the windows is not defined (that is, the PCI_PROP_IO_REGS property is a single PciPropIoRegs structure), the bus bridge will not forward transactions of a corresponding type from primary to secondary busses. If the PCI_PROP_IO_REGS property is not specified at all, the bus bridge will not forward I/O access transactions from primary to secondary busses.
The PCI_PROP_MEM_RGN property specifies a window (within 32-bit PCI address space) for pre-fetchable memory access. Transactions issued on the primary bus will be claimed by the bus bridge and forwarded to the secondary bus, if they fall into this address window.
The PCI64_PROP_MEM_RGN property specifies a window (within 64-bit PCI address space) for pre-fetchable memory access. Transactions issued on the primary bus will be claimed by the bus bridge and forwarded to the secondary bus, if they fall into this address window.
Note that the PCI_PROP_MEM_RGN and PCI64_PROP_MEM_RGN properties are mutually exclusive. In other words, only one of them can be specified.
Access transactions issued on the secondary bus which do not fall into the windows specified by the PCI_PROP_IO_REGS and PCI_PROP_MEM_RGN (or PCI64_PROP_MEM_RGN) properties will be forwarded by the bus bridge to the primary bus.
The D2115X_PROP_INTR_CONF property specifies the pci interrupts routing on the secondary bus. The property value has the D2115xPropIntrConf type. D2115xPropIntrConf is a two dimensional matrix mapping secondary bus pci interrupts to the primary bus pci interrupts depending on the device number. In other words, for each secondary interrupt (PCI_INTR_A/B/C/D) and device number (0..31) pair, the matrix element specifies the primary bus interrupt (PCI_INTR_A/B/C/D). If a matrix element is zero, the corresponding interrupt (for the corresponding device number) is not routed to the primary bus. The bus driver will return the K_EFAIL error code if an attempt is made to connect a handler to such an interrupt source.
If the D2115X_PROP_INTR_CONF property is not specified, a rotated interrupt routing is implemented by the bus driver. There is a one-to-one correspondence between the secondary and primary pci interrupts for the device zero. For the next device, the primary interrupts are rotated and so on. For example, the interrupts routing shown below is applied to the two:
secondary bus interrupt |
primary bus interrupt |
PCI_INTR_A | PCI_INTR_C |
PCI_INTR_B | PCI_INTR_D |
PCI_INTR_C | PCI_INTR_A |
PCI_INTR_D | PCI_INTR_B |
The D2115X_PROP_CONF property specifies the configuration of the dec2115x pci-to-pci bridge. The D2115xPropConf structure consists of images of the bridge configuration registers. If the D2115X_PROP_CONF property is specified, the driver will program configuration registers according to the images given by the D2115xPropConf structure. Otherwise, the default values will be used. The Table below shows the D2115xPropConf fields and the default values used for the bridge configuration when the D2115X_PROP_CONF property is not specified.
type | name | default | addr | description |
uint8_f | cline_size | 00 | 0c | cache line size |
uint8_f | plat_timer | 00 | 0d | primary latency timer |
uint8_f | slat_timer | 00 | 1b | secondary latency timer |
uint8_f | chip_ct1 | 00 | 40 | chip control |
uint8_f | gpio_cfg | 00 | 66 | GPIO output enable (*) |
uint8_f | serr_dis | 00 | 64 | primary SERR# event disable |
uint16_f | bridge_ct1 | 0023 | 3e | bridge control |
uint16_f | arbiter_ct1 | 0200 | 43 | arbiter control |
uint16_f | sclock_ctl | 0000 | 68 | secondary clock output control |
(*) the gpio_cfg field is ignored for the dec21152 bridge.
The following bits (defined by dec2115x.h) can be set in the chip_ctl field:
D2115X_CTRL_LINS -- live insertion mode
TRL_NPREF -- secondary bus memory pre-fetch disable
D2115X_CTRL_WDIS -- write disconnect on cache line boundary
The following bits (defined by dec2115x.h) can be set in the serr_dis field:
D2115X_SED_PW_PE -- posted write parity error
D2115X_SED_PW_ND - posted write non delivery
D2115X_SED_PW_TA - posted write target abort
D2115X_SED_PW_MA - posted write master abort
D2115X_SED_DW_ND - delayed write non delivery
D2115X_SED_DR_ND - delayed read no data
D2115X_SED_DT_MA - delayed transaction MA
The following bits (defined by pci.h and dec2115.h) can be set in the bridge_ctl field:
PCI_PCI_CTL_PARERR_RESP - parity error response
PCI_PCI_CTL_SYSERR - SERR# forwarding
PCI_PCI_CTL_MABORT_MODE - master abort mode
D2115X_PCI_CTL_PMTO - primary master time-out
D2115X_PCI_CTL_SMTO - secondary master time-out
D2115X_PCI_CTL_MTO_SERR_EN - master time-out SERR# enable
See the Intel 2115x PCI-to-PCI Bridge Datasheet for programming the bus bridge configuration registers (http://www.intel.com).
Current version of the dec2115x driver does not support the dynamic assignment of the PCI bus resources.
See attributes(5) for descriptions of the following attributes:
ATTRIBUTE TYPE | ATTRIBUTE VALUE |
---|---|
Interface Stability | Evolving |
NAME | SYNOPSIS | FEATURES | DESCRIPTION | RESTRICTIONS | ATTRIBUTES | SEE ALSO