NAME | SYNOPSIS | FEATURES | DESCRIPTION | RESTRICTIONS | ATTRIBUTES | SEE ALSO
drv_f/src/quicc/8xx/quicc8xx.h - mpc8xx specific constants drv_f/src/quicc/8xx/quicc8xx.c - driver code drv_f/src/quicc/8xx/quicc8xxProp.h - driver specific properties
DRV
The quicc8xx bus driver implements:
the common bus driver interface
the quicc bus driver interface
The driver works on Motorola mpc8xx micro-controllers and provides an abstraction of the CPM peripheral bus and the external U-BUS.
The driver uses the PowerPC specific dki interface provided by the kernel. Thus, the driver works only with PowerPC family products.
The quicc8xx driver does not provide the drv_probe() routine. In other words, the quicc8xx driver does not enumerate the bus, nor does it detect a quicc8xx device or create an associated device node. When the quicc8xx driver is used, associated device nodes should be created either statically by a boot program or dynamically by a separate bus enumerator driver. Such an enumerator driver could be developed for this particular bus architecture.
The quicc8xx driver provides the drv_bind() routine. This routine examines the device node property PROP_NODE in order to recognize a quicc8xx compatible device. This routine checks whether the device node name matches a pre-defined device name. If the check is positive, the drv_bind() routine binds the driver to the device node attaching a PROP_DRIVER property to the device node. The property value specifies the quicc8xx driver name. The parent bus driver uses such a property to determine the name of the driver servicing the device. In other words, via the PROP_DRIVER property, the driver gives its name to the parent bus driver asking it to invoke the drv_init() routine on that device. Note that the drv_bind() routine does nothing if a PROP_DRIVER property is already present in the device node. In other words, the drv_bind()routine does not override existing driver-to-device binding.
The driver does not provide the drv_unload() entry. Thus, the driver component cannot be unloaded, even if it has been dynamically loaded at run time.
The driver supports the DKI_SYS_SHUTDOWN event specified by the common dki interface.
The Table below summarizes characteristics of the quicc8xx bus driver.
driver name: | "sun:powerpc-mpc8xx-(bus, quicc)" |
hardware: | Motorola MPC8xx micro-controllers |
exported interface: | "quicc" (QUICC_CLASS) |
exported interface version: | 0 (QUICC_VERSION_INITIAL) |
imported parent interface: | "powerpc" (FDKI_CLASS) |
minimal parent interface version: | 0 (FDKI_VERSION_INITIAL) |
device probing (auto-detection): | not supported |
driver to device binding: | supported (on node name basis) |
driver unloading: | not supported |
system (emergency) shut-down: | supported |
normal device shut-down: | not supported |
hot-plug (surprise) device removal: | not supported |
The Table below lists device node properties used by the quicc8xx driver. Note that the column "m/o" specifies whether a given property is mandatory or optional. For optional properties, the column "default value" shows a default value which is used by the driver when a given property is not specified.
Name | Alias | Type | m/o | Default Value |
---|---|---|---|---|
"imap-rgn" | QUICC_PROP_IMAP_RGN | QuiccPropMemRgn | m | |
"dpram-rgn" | QUICC_PROP_DPRAM_RGN | QuiccPropMemRgn | m | |
"clock-freq" | QUICC_PROP_CLOCK_FREQ | QuickPropClockFreq | m | |
"brg-clock-freq" | QUICC_PROP_BRG_CLOCK_FREQ | QuiccPropClockFreq | m | |
"cpm"-clock-freq" | QUICC_PROP_CPMCLK | QuiccPropClockFreq | m | |
"mem-rgn | QUICC_PROP_MEM_RGN | QuiccPropMemRgn | o | see text |
"pin-config" | QUICC_8xx_PROP_PIN_CONFIG | Quicc8xxPropPinConfig | m | |
"intr-config" | QUICC_8xx_PROP_INTR_CONFIG | Quicc8xxPropIntrConfig | o | see text |
The QUICC_PROP_IMAP_RGN property specifies the internal memory region mapping.
The QUICC_PROP_DPRAM_RGN property specifies the Dual Ported RAM memory region mapping.
The QUICC_PROP_CLOCK_FREQ property specifies the local bus clock frequency.
The QUICC_PROP_CPM_CLOCK_FREQ property specifies the CPM processor clock frequency.
The QUICC_PROP_BRG_CLOCK_FREQ property specifies the BRGs input clock frequency.
The QUICC_PROP_MEM_RGN property specifies the regions in the internal memory map where allocation of DMA regions is allowed. This property is an array that declares the ranges of memory, in the internal memory map, which are free for DMA usage (dma_alloc()/dma_free()). By default, the entire DPRAM region of the internal memory map is usable for DMA allocation purposes.
The QUICC_8XX_PROP_PIN_CONFIG property specifies the configuration and routing of the parallel I/O ports. This property provides the values to be set in internal map registers which manage the configuration and routing of parallel I/O port pins. For each port (A, B, C, D), the following registers must be provided:
Pin assignment register.
Data direction register.
Open drain, or special option when existing for a port.
Data register value. Note that port data register is set only if the provided value is not zero.
In addition, the following SI registers must be provided:
SI mode register is used to configure SMC in multiplexed or non-multiplexed mode (NMSI), and to select SMC clocks.
SI clock route register is used to configure SCC devices in multiplexed or non-multiplexed mode (NMSI), and to select SCC clocks
The QUICC_8XX_PROP_INTR_CONFIG property specifies the interrupts configuration. This property defines :
the priority (ranging from lowest SIU_PRIO_0 to highest SIU_PRIO_7) of each SIU internal source of interrupt :
time base
periodic interrupt timer
real time clock
PMCIA card A interrupt request and status changed sources
PMCIA card B interrupt request and status changed sources
cpm interrupt sources
the interrupt configuration for CPM interrupt sources
The "cpmIntrConfig" property field should be set using the following macro:
CPM_INTR_CONFIG(scc_prio_mode, scc_p0, scc_p1, scc_p2, scc_p3, highest)
scc_prio_mode indicates the SCC priority mode to use in:
SCC_PRIO_GROUPED: SCC interrupts are grouped by priority in higher priorities
SCC_PRIO_SPREAD: SCC interrupts are spread by priority among other sources
scc_p0,1,2,3 indicates which SCC device (in 1 to 4) is assigned to each of the four available SCC priority levels (from lowest scc_p0 to highest scc_p3).
highest indicates a value of type QuiccPropIntr which should be assigned to the highest CPM priority.
Default settings for SIU interrupt priorities are:
time base | not set |
periodic interrupt timer | not set |
real time clock | not set |
PMCIA card A interrupt request | not set |
PMCIA card A status changed | not set |
PMCIA card B interrupt request | not set |
PMCIA card B status changed | not set |
cpm | SIU_PRIO_4 |
cpm interrupt configuration is set to: CPM_INTR_CONFIG(SCC_PRIO_SPREAD, 4, 3, 2, 1, QUICC_PC15_INTR).
The current version of the quicc8xx driver does not support dynamic assignment of quicc bus reources. The quicc8xx driver does not implement I/O pin management services (io_pin_attach).
See attributes(5) for descriptions of the following attributes:
ATTRIBUTE TYPE | ATTRIBUTE VALUE |
---|---|
Interface Stability | Evolving |
NAME | SYNOPSIS | FEATURES | DESCRIPTION | RESTRICTIONS | ATTRIBUTES | SEE ALSO