Chip Multi-Threading Test ( cmttest )
cmttest verifies the proper functioning of the multiprocessor hardware with multiple cores in one CPU. cmttest tests the path between the cores on the same CPU in addition to performing CPU specific testing. cmttest uses the Cache Coherence, Shared Memory, and RAM subtests. The Cache Coherence subtest is used to test the coherence among all of the Cores in a CMT (Chip Multiprocessor). The Shared Memory subtest is used to test the shared memory among all the cores in a CMT. The RAM subtest is used to test the memory. The RAM subtest covers TLB, MMU, and bus balancing. The Interrupt subtest covers the intra-core and inter-core interrupt generation and receiving logic.Only one cmttest is registered and cmttest is present under the logical name Processor(s). There is no physical name provided. The probe routine of cmttest probes all CMTs in which at least two cores are online.
cmttest was named cmptest in previous SunVTS releases.
cmttest Options
To reach the dialog box below, right-click on the test name in the System Map and select Test Parameter Options. If you do not see this test in the System Map, you might need to expand the collapsed groups, or your system may not include the device appropriate to this test. Refer to the SunVTS User's Guide for more details.
FIGURE 3-1 cmttest Test Parameter Options Dialog Box
The processors that can be tested are listed in the Configuration area of the menu. You can enable or disable the multiprocessing test for individual processors on this menu.
The options listed in the following table can be run alone or concurrently with other options.
TABLE 3-1 cmttest Options
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cmttest Options
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Description
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CMTS
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You can test specific CMTs by clicking Select on the check boxes to enable or disable each CMT. A check mark indicates the CMT is enabled for testing. The default setting is all CMTs enabled.
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Perf Counters
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By default performance monitoring is disabled. When performance monitoring is Enabled tests print memory bandwidth achieved while testing. Right now only ram subtest has the counters built in. Bandwidth calculations assume that all banks corresponding to all cpus are present and had same number of reads and writes. (Note: Perfcounter monitoring can be done on SUNW,UltraSPARC-IV processors, If user tries to enable perfCounter, and perfcounters are not supported ,on cpus the appropriate warning message is displayed, with disabling the perfcounter.)
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ECC Monitor
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This option is used to Enable or Disable ECC error monitoring. The default option is Disabled.
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ECC Threshold
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Range is [0-255].This determines how many correctable ECC errors occurred in the elapsed time before cmttest reports a test failure. The default threshold value is 1.
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Strand Level Test
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For processors like Niagara with multiple strands per core, the test selects one strand/core to perform testing. This behavior can be changed by setting this option to Yes. The default setting No does the most optimal testing and hence should be used in general.The interrupt subtest will not be run if this option is set to Yes. This option doesnt have any effect on non-multistranded processors such as the UltraSPARC IV+.
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cmttest Test Modes
TABLE 3-2 cmttest Supported Test Modes
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Test Mode
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Description
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Functional
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The Functional test mode is supported.
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Exclusive
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Performs the full test.
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cmttest Command-Line Syntax
For 32-bit configurations:
/opt/SUNWvts/bin/cmttest standard_arguments
-o cmts=0+1+2..., em=Enabled|Disabled, threshold=[0-255], perf=Enabled|Disabled, strandleveltest=Yes|No
For 64-bit configurations:
/opt/SUNWvts/bin/sparcv9/cmttest standard_arguments
-o cmts=0+1+2..., em=Enabled|Disabled, threshold=[0-255], perf=Enabled|Disabled, strandleveltest=Yes|No
TABLE 3-3 cmttest Command-Line Syntax
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Arguments Description
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cmts=0+1+2...
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0, 1, 2,... mentions the CPU ID of any one core of the CMTs to be tested. To display on the GUI, CPU ID of core 0 is taken as the identifier for a CMT. For displaying the Error/INFO/LOG messages, the CPU ID of the core 0 is used. For multistranded processors such as the Niagara, if more than one strand from a core is selected, only one of them is used for testing. To override this behavior,the option strandleveltest must be set to Yes.
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em=Enabled|Disabled
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Enable or Disable ECC error monitoring. The default value is Disabled.
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threshold=[0-255]
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Determines how many correctable ECC errors can occur in the elapsed time before cmttest reports a test failure. The range is [0-255]. The default value is 1.
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perf=Enabled|Disabled
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By default performance monitoring is Disabled. When performance monitoring is Enabled tests print memory bandwidth achieved while testing. Only the RAM subtest has the counters built in. Bandwidth calculations assume that all banks corresponding to all CPUs are present and have the same number of reads and writes.Note: Perfcounter monitoring can be done on SUNW, UltraSPARC IV processors. If you try to enable perfCounter, and the perfcounters are not supported on the CPUs, the appropriate warning message is displayed and the perfcounter is disabled.
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strandleveltest=Yes|No
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This option is used for strand level testing for multi-stranded processors such as the Niagara. Selecting Yes for this option, selects all strands for testing.
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Note -
64-bit tests are located in the sparcv9 subdirectory: /opt/SUNWvts/bin/sparcv9/testname, or the relative path to which you installed SunVTS. If a test is not present in this directory, then it may only be available as a 32-bit test. For more information refer to the "32-Bit and 64-Bit Tests" section of the SunVTS 5.1 Test Reference Manual (816-5145-10).
