C H A P T E R 6

Running POST

Each of the system boards (CPU/Memory boards and IB_SSC assembly) contains a flash PROM that provides storage for power-on self-test (POST) diagnostics. POST tests the following:

CPU chips

External cache

Memory

Bus interconnect

I/O ASICs

I/O buses

POST provides several diagnostic levels that can be selected using the OpenBoot PROM variable diag-level. In addition, the bootmode command enables the POST settings to be declared for the next system reboot.

There is a separate POST that runs on the SC, which can be controlled using the setupsc command.

This chapter includes the following topics:

OpenBoot PROM Variables for POST Configuration

Controlling POST With the bootmode Command

Controlling the System Controller POST

OpenBoot PROM Variables for POST Configuration

The OpenBoot PROM enables you to set variables that configure how POST runs. These are described in the OpenBoot 4.x Command Reference Manual.

You can use the OpenBoot printenv command to display the current settings:

{3} ok printenv diag-level

diag-level								init				(init)

You can use the OpenBoot PROM setenv command to change the current setting of a variable:

{1} ok setenv diag-level quick

diag-level=quick

For example, you can configure POST to run faster by using:

{1} ok setenv diag-level init

diag-level=init

{1} ok setenv verbosity-level off

verbosity-level=off

This has the same effect as using the SC command
bootmode skipdiag at the LOM prompt. The difference is that by using the OpenBoot command the settings remain permanent until you change them again.

TABLE 6-1 POST Configuration Parameters
Parameter	Value	Description
`diag-level`	`init` (default value)	Only system board initialization code is run. No testing is done. This is a very fast pass through POST.
	`quick`	All system board components are tested using few tests with few test patterns.
	min	Core functionalities of all system board components are tested. This testing performs a quick sanity check of the devices under test.
	`max`	All system board components are tested with all tests and test patterns, except for memory and Ecache modules. For memory and Ecache modules, all locations are tested with multiple patterns. More extensive, time-consuming algorithms are not run at this level.
	`mem1`	Runs all tests at the default level plus more exhaustive DRAM and SRAM test algorithms.
	`mem2`	This is the same as `mem1` with the addition of a DRAM test that does explicit compare operations of the DRAM data.
`verbosity-level`	`off`	No status messages are displayed.
	`min` (default value)	Test names status messages, and error messages are displayed.
	`max`	Subtest trace messages are displayed.
`error-level`	`off`	No error messages are displayed.
	`min`	The failing test name is displayed.
	`max` (default value)	All relevant error statuses are displayed.
`interleave-scope`	`within-board` (default value)	The memory banks on a system board will be interleaved with each other.
	`across-boards`	The memory will be interleaved on all memory banks across all of the boards in the system.
`interleave-mode`	optimal (default value)	The memory is mixed-size interleaving in order to gain optimal performance.
	`fixed`	The memory is fixed-size interleaving.
	`off`	There is no memory interleaving.
`reboot-on-error`	false (default value)	The system is paused when there is an error.
	`true`	The system is rebooted.
`use-nvramrc?`		This parameter is the same as the OpenBoot PROM `nvramrc?` parameter. This parameter uses aliases that are stored in `nvramrc`.
	`true`	The OpenBoot PROM executes the script stored in `nvramrc` if this parameter is set to `true`.
	`false` (default value)	The OpenBoot PROM does not evaluate the script stored in `nvramrc` if this parameter is set to `false`.
`auto-boot?`		Controls booting of the Solaris Operating System.
	`true` (default value)	If this value is `true`, the system boots automatically after POST has run.
	`false`	If this parameter value is set to `false`, you will obtain the OpenBoot PROM ok prompt after POST runs, from which you must type a `boot` command to boot the Solaris Operating System.
`error-reset-recovery`		Controls the behavior of the system after an externally initiated reset (XIR) as well as a red mode trap.
	`sync` (default value)	The OpenBoot PROM invokes `sync`. A core file is generated. If the invocation returns, the OpenBoot PROM performs a reboot.
	`none`	The OpenBoot PROM prints a message describing the reset trap that triggered the error reset and passes control to the OpenBoot PROM ok prompt. The message describing the reset trap type is platform-specific.
	`boot`	The OpenBoot PROM firmware reboots the system. A core file is not generated. Rebooting a system occurs using the OpenBoot PROM settings for diag-device or boot-device, depending on the value of the OpenBoot PROM configuration variable `diag-switch?` If diag-switch? is set to `true`, the device names in diag-device will be the default for boot. If diag-switch? is set to `false`, the device names in boot-device will be the default for boot.

The default output from POST is similar to CODE EXAMPLE 6-1.

CODE EXAMPLE 6-1 POST Output Using `max` Setting
Testing CPU Boards ... Loading the test table from board SB0 PROM 0 ... {/N0/SB0/P0} Running CPU POR and Set Clocks {/N0/SB0/P1} Running CPU POR and Set Clocks {/N0/SB0/P2} Running CPU POR and Set Clocks {/N0/SB0/P3} Running CPU POR and Set Clocks {/N0/SB0/P0} @(#) lpost 5.13.0007 2002/07/18 12:45 {/N0/SB0/P2} @(#) lpost 5.13.0007 2002/07/18 12:45 {/N0/SB0/P1} @(#) lpost 5.13.0007 2002/07/18 12:45 {/N0/SB0/P0} Copyright 2001 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P0} Subtest: Setting Fireplane Config Registers {/N0/SB0/P0} Subtest: Display CPU Version, frequency {/N0/SB0/P0} Version register = 003e0015.21000507 {/N0/SB0/P0} Cpu/System ratio = 6, cpu actual frequency = 900 {/N0/SB0/P1} Copyright 2001 Sun Microsystems, Inc. All rights reserved. . . . . . . . . . <more POST ouput> . . . . . . pci bootbus-controller pci Probing /ssm@0,0/pci@18,700000 Device 1 Nothing there Probing /ssm@0,0/pci@18,700000 Device 2 Nothing there Probing /ssm@0,0/pci@18,700000 Device 3 ide disk cdrom Probing /ssm@0,0/pci@18,600000 Device 1 Nothing there Probing /ssm@0,0/pci@18,600000 Device 2 scsi disk tape scsi disk tape pci pci Probing /ssm@0,0/pci@19,700000 Device 1 Nothing there Probing /ssm@0,0/pci@19,700000 Device 2 Nothing there Probing /ssm@0,0/pci@19,700000 Device 3 Nothing there Probing /ssm@0,0/pci@19,600000 Device 1 network Probing /ssm@0,0/pci@19,600000 Device 2 network Sun Fire V1280 OpenFirmware version 5.13.0007 (07/18/02 12:45) Copyright 2001 Sun Microsystems, Inc. All rights reserved. SmartFirmware, Copyright (C) 1996-2001. All rights reserved. 16384 MB memory installed, Serial #9537054. Ethernet address 8:0:xx:xx:xx:xx, Host ID: 80xxxxxx. NOTICE: obp_main: Extended diagnostics are now switched on. {0} ok

CODE EXAMPLE 6-1 POST Output Using max Setting

Testing CPU Boards ...

Loading the test table from board SB0 PROM 0 ...

{/N0/SB0/P0} Running CPU POR and Set Clocks

{/N0/SB0/P1} Running CPU POR and Set Clocks

{/N0/SB0/P2} Running CPU POR and Set Clocks

{/N0/SB0/P3} Running CPU POR and Set Clocks

{/N0/SB0/P0} @(#) lpost 5.13.0007       2002/07/18 12:45

{/N0/SB0/P2} @(#) lpost 5.13.0007       2002/07/18 12:45

{/N0/SB0/P1} @(#) lpost 5.13.0007       2002/07/18 12:45

{/N0/SB0/P0} Copyright 2001 Sun Microsystems, Inc. All rights reserved.

{/N0/SB0/P0} Subtest: Setting Fireplane Config Registers

{/N0/SB0/P0} Subtest: Display CPU Version, frequency

{/N0/SB0/P0} Version register = 003e0015.21000507

{/N0/SB0/P0} Cpu/System ratio = 6, cpu actual frequency = 900

{/N0/SB0/P1} Copyright 2001 Sun Microsystems, Inc. All rights reserved.

. . .

. . .

. . . <more POST ouput>

. . .

. . .

pci bootbus-controller pci

Probing /ssm@0,0/pci@18,700000 Device 1  Nothing there

Probing /ssm@0,0/pci@18,700000 Device 2  Nothing there

Probing /ssm@0,0/pci@18,700000 Device 3  ide disk cdrom

Probing /ssm@0,0/pci@18,600000 Device 1  Nothing there

Probing /ssm@0,0/pci@18,600000 Device 2  scsi disk tape scsi disk tape

pci pci

Probing /ssm@0,0/pci@19,700000 Device 1  Nothing there

Probing /ssm@0,0/pci@19,700000 Device 2  Nothing there

Probing /ssm@0,0/pci@19,700000 Device 3  Nothing there

Probing /ssm@0,0/pci@19,600000 Device 1  network

Probing /ssm@0,0/pci@19,600000 Device 2  network

Sun Fire V1280

OpenFirmware version 5.13.0007 (07/18/02 12:45)

Copyright 2001 Sun Microsystems, Inc.  All rights reserved.

SmartFirmware, Copyright (C) 1996-2001.  All rights reserved.

16384 MB memory installed, Serial #9537054.

Ethernet address 8:0:xx:xx:xx:xx, Host ID: 80xxxxxx.

NOTICE: obp_main: Extended diagnostics are now switched on.

{0} ok

Controlling POST With the `bootmode` Command

The SC bootmode command allows you to specify the boot configuration for the next system reboot only. This removes the necessity for taking the system down to the OpenBoot PROM to make these changes, for instance to the diag-level variable.

For example, use the following commands to force the highest level of POST tests to be run prior to the next reboot:

lom>shutdown

lom>bootmode diag

lom>poweron

To force the lowest level of POST tests to be run prior to the next reboot, use:

lom>shutdown

lom>bootmode skipdiag

lom>poweron

If the system is not rebooted within 10 minutes of the bootmode command being issued, the bootmode setting is returned to normal and the previously-set values of diag-level and verbosity-level are applied.

For a fuller description of these commands, see the Sun Fire Entry-Level Midrange System Controller Command Reference Manual.

Controlling the System Controller POST

The SC power-on self-test is configured using the LOM setupsc command. This enables the SC POST level to be set to off, min or max. For a fuller description of this command, see the Sun Fire Entry-Level Midrange System Controller Command Reference Manual.

SC POST output appears only on the SC serial connection.

To set the SC POST diagnostic level default to min:

CODE EXAMPLE 6-2 Setting SC POST Diagnostic Level to `min`
lom>setupsc System Controller Configuration ------------------------------- SC POST diag Level [off]: min Host Watchdog [enabled]: Log Reset Data [true]: Verbose Reset Data [true]: Rocker Switch [enabled]: Secure Mode [off]: PROC RTUs installed: 8 PROC Headroom Quantity (0 to disable, 4 MAX) [0]: Tolerate correctable memory errors [false]: lom>

CODE EXAMPLE 6-2 Setting SC POST Diagnostic Level to min

lom>setupsc

 System Controller Configuration

 -------------------------------

 SC POST diag Level [off]: min

 Host Watchdog [enabled]:

 Log Reset Data [true]:

 Verbose Reset Data [true]:

 Rocker Switch [enabled]:

 Secure Mode [off]:

 PROC RTUs installed: 8

 PROC Headroom Quantity (0 to disable, 4 MAX) [0]:

 Tolerate correctable memory errors [false]:

 lom>

When SC POST diag-level is set to min you see the following output on the serial port whenever the SC is reset:

CODE EXAMPLE 6-3 SC POST Output With Diagnostic Level Set to `min`
@(#) SYSTEM CONTROLLER(SC) POST 21 2001/12/11 17:11 PSR = 0x044010e5 PCR = 0x04004000 SelfTest running at DiagLevel:0x20 SC Boot PROM Test BootPROM CheckSum Test IU Test IU instruction set Test Little endian access Test FPU Test FPU instruction set Test SparcReferenceMMU Test SRMMU TLB RAM Test SRMMU TLB Read miss Test SRMMU page probe Test SRMMU segment probe Test SRMMU region probe Test SRMMU context probe Test . . . . . . . . . <more SCPOST ouput> . . . . . . Local I2C AT24C64 Test EEPROM Device Test performing eeprom sequential read Local I2C PCF8591 Test VOLT_AD Device Test channel[00000001] Voltage(0x00000099) :1.49 channel[00000002] Voltage(0x0000009D) :3.37 channel[00000003] Voltage(0x0000009A) :5.1 channel[00000004] Voltage(0x00000000) :0.0 Local I2C LM75 Test TEMP0(IIep) Device Test Temparature : 24.50 Degree(C) Local I2C LM75 Test TEMP1(Rio) Device Test Temparature : 23.50 Degree(C) Local I2C LM75 Test TEMP2(CBH) Device Test Temparature : 32.0 Degree(C) Local I2C PCF8574 Test Sc CSR Device Test Console Bus Hub Test CBH Register Access Test POST Complete.

CODE EXAMPLE 6-3 SC POST Output With Diagnostic Level Set to min

@(#) SYSTEM CONTROLLER(SC) POST 21 2001/12/11 17:11

PSR = 0x044010e5

PCR = 0x04004000

        SelfTest running at DiagLevel:0x20

SC Boot PROM             Test

        BootPROM CheckSum               Test

IU        Test

        IU instruction set              Test

        Little endian access            Test

FPU       Test

        FPU instruction set             Test

SparcReferenceMMU     Test

        SRMMU TLB RAM                   Test

        SRMMU TLB Read miss             Test

        SRMMU page    probe             Test

        SRMMU segment probe             Test

        SRMMU region  probe             Test

        SRMMU context probe             Test

. . .

. . .

. . . <more SCPOST ouput>

. . .

. . .

Local I2C AT24C64     Test

        EEPROM       Device             Test

        performing eeprom sequential read

Local I2C PCF8591     Test

        VOLT_AD      Device             Test

        channel[00000001] Voltage(0x00000099) :1.49

        channel[00000002] Voltage(0x0000009D) :3.37

        channel[00000003] Voltage(0x0000009A) :5.1

        channel[00000004] Voltage(0x00000000) :0.0

Local I2C LM75        Test

        TEMP0(IIep)  Device             Test

        Temparature : 24.50 Degree(C)

Local I2C LM75        Test

        TEMP1(Rio)   Device             Test

        Temparature : 23.50 Degree(C)

Local I2C LM75        Test

        TEMP2(CBH)   Device             Test

        Temparature : 32.0 Degree(C)

Local I2C PCF8574     Test

        Sc CSR       Device             Test

Console Bus Hub         Test

        CBH Register Access             Test

POST Complete.

OpenBoot PROM Variables for POST Configuration

Controlling POST With the bootmode Command

Controlling the System Controller POST

Controlling POST With the `bootmode` Command