A P P E N D I X  A

BIOS Event Logs and POST Codes

This appendix contains information about BIOS event logs, power-on self test (POST), and console redirection.



Note - This chapter applies to all Sun Fire X4100/X4100 M2 and X4200/X4200 M2 servers, unless otherwise noted.




Viewing BIOS Event Logs

Use this procedure to view the BIOS event log and the BMC system event log:

1. To turn on main power mode (all components powered on), use a ball-point pen or other stylus to press and release the Power button on the server front panel. See FIGURE 1-1 or FIGURE 1-2.

When main power is applied to the full server, the Power/OK LED next to the Power button lights and remains lit.

2. Enter the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

The BIOS Main menu screen is displayed.

3. View the BIOS event log:

a. From the BIOS Main Menu screen, select Advanced.

The Advanced Settings screen is displayed.

b. From the Advanced Settings screen, select Event Log Configuration.

The Advanced Menu Event Logging screen is displayed.

c. From the Event Logging Details screen, select View Event Log.

All unread events are displayed.

4. View the BMC system event log:

a. From the BIOS Main Menu screen, select Advanced.

The Advanced Settings screen is displayed.

b. From the Advanced Settings screen, select IPMI 2.0 Configuration.

The Advanced Menu IPMI 2.0 Configuration screen is displayed:

c. From the IPMI 2.0 Configuration screen, select View BMC System Event Log.

The log takes about 60 seconds to generate, then it is displayed on the screen.

 

5. If the problem with the server is not evident, continue with Using the ILOM SP GUI to View System Information, or Using IPMItool to View System Information.


Power-On Self-Test (POST)

The system BIOS provides a rudimentary power-on self-test. The basic devices required for the server to operate are checked, memory is tested, the LSI 1064 disk controller and attached disks are probed and enumerated, and the two Intel dual-gigabit Ethernet controllers are initialized.

The progress of the self-test is indicated by a series of POST codes. These codes are displayed at the bottom right corner of the system's VGA screen (once the self-test has progressed far enough to initialize the system video). However, the codes are displayed as the self-test runs and scroll off of the screen too quickly to be read. An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Redirecting Console Output).

How BIOS POST Memory Testing Works

The BIOS POST memory testing is performed as follows:

1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is shadowed (that is, copied from ROM to DRAM).

2. Once executing out of DRAM, the BIOS performs a simple memory test (a write/read of every location with the pattern 55aa55aa).



Note - This memory test is performed only if Quick Boot is not enabled from the Boot Settings Configuration screen. Enabling Quick Boot causes the BIOS to skip the memory test. See Changing POST Options for more information.



3. The BIOS polls the memory controllers for both correctable and uncorrectable memory errors and logs those errors into the service processor.

Redirecting Console Output

Use these instructions to access the service processor and redirect the console output so that the BIOS POST codes can be read.

1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

The BIOS Main menu screen is displayed.

2. When the BIOS Main menu screen is displayed, select Advanced.

3. When the Advanced Settings screen is displayed, select IPMI 2.0 Configuration.

4. When the IPMI 2.0 Configuration screen is displayed, select the LAN Configuration menu item.

5. Select the IP Address menu item.

The service processor's IP address is displayed using the following format:
Current IP address in BMC : xxx.xxx.xxx.xxx

6. Start a web browser and type the service processor's IP address in the browser's URL field.

7. When you are prompted, for a user name and password, type the following:

8. When the ILOM Service Processor web GUI screen is displayed, click the Remote Control tab.

9. Click the Redirection tab.

10. Set the color depth for the redirection console at either 6 or 8 bits.

11. Click the Start Redirection button.

12. When you are prompted for a user name and password, type the following:

The current POST screen is displayed.

Changing POST Options

These instructions are optional, but you can use them to change the operations that the server performs during POST testing.

1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

The BIOS Main menu screen is displayed.

2. When the BIOS Main menu screen is displayed, select Boot.

The Boot Settings screen is displayed.

3. When the Boot Settings screen is displayed, select Boot Settings Configuration.

The Boot Settings Configuration screen is displayed.

4. On the Boot Settings Configuration screen, there are several options that you can enable or disable:

POST Codes

TABLE A-1 contains descriptions of each of the POST codes, listed in the same order in which they are generated. These POST codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST codes listed in TABLE A-1, the first two digits are from port 81 and the last two digits are from port 80.

 


TABLE A-1 POST Codes

Post Code

Description

00d0

Coming out of POR, PCI configuration space initialization, Enabling the AMD controller's SMBus.

00d1

Keyboard controller BAT, Waking up from PM, Saving power-on CPUID in scratch CMOS.

00d2

Disable cache, full memory sizing, and verify that flat mode is enabled.

00d3

Memory detections and sizing in boot block, cache disabled, IO APIC enabled.

01d4

Test base 512KB memory. Adjust policies and cache first 8MB.

01d5

Bootblock code is copied from ROM to lower RAM. BIOS is now executing out of RAM.

01d6

Key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.

01d7

Restoring CPUID; moving bootblock-runtime interface module to RAM; determine whether to execute serial flash.

01d8

Uncompressing runtime module into RAM. Storing CPUID information in memory.

01d9

Copying main BIOS into memory.

01da

Giving control to BIOS POST.

0004

Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default values.

00c2

Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.

00c3

Errata workarounds applied to the BSP (#78 & #110).

00c6

Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate.

00c7

HT sets link frequencies and widths to their final values.

000a

Initializing the 8042 compatible Keyboard Controller.

000c

Detecting the presence of Keyboard in KBC port.

000e

Testing and initialization of different Input Devices. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.

8600

Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.

de00

Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.

8613

Initialize PM regs and PM PCI regs at Early-POST. Initialize multi host bridge, if system supports it. Setup ECC options before memory clearing. Enable PCI-X clock lines in the AMD controller.

0024

Uncompress and initialize any platform specific BIOS modules.

862a

BBS ROM initialization.

002a

Generic Device Initialization Manager (DIM) - Disable all devices.

042a

ISA PnP devices - Disable all devices.

052a

PCI devices - Disable all devices.

122a

ISA devices - Static device initialization.

152a

PCI devices - Static device initialization.

252a

PCI devices - Output device initialization.

202c

Initializing different devices. Detecting and initializing the video adapter installed in the system that have optional ROMs.

002e

Initializing all the output devices.

0033

Initializing the silent boot module. Set the window for displaying text information.

0037

Displaying sign-on message, CPU information, setup key message, and any OEM specific information.

4538

PCI devices - IPL device initialization.

5538

PCI devices - General device initialization.

8600

Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.


POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. TABLE A-2 describes the type of checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80.

 


TABLE A-2 POST Code Checkpoints

Post Code

Description

03

Disable NMI, Parity, video for EGA, and DMA controllers. At this point, only ROM accesses are to the GPNV. If BB size is 64K, require to turn on ROM Decode below FFFF0000h. It should allow USB to run in E000 segment. The HT must program the NB specific initialization and OEM specific initialization can program if it need at beginning of BIOS POST, like overriding the default values of Kernel Variables.

04

Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system.

05

Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.

06

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock."

C0

Early CPU Init Start--Disable Cache--Init Local APIC.

C1

Set up boot strap processor information.

C2

Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.

C3

Errata workarounds applied to the BSP (#78 & #110).

C5

Enumerate and set up application processors. This includes microcode loading, and workarounds for errata (#78, #110, #106, #107, #69, #63).

C6

Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs are left in the CLI HLT state.

C7

The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming.

0A

Initializes the 8042 compatible Keyboard Controller.

0B

Detects the presence of PS/2 mouse.

0C

Detects the presence of Keyboard in KBC port.

0E

Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.

13

Initialize PM regs and PM PCI regs at Early-POST, Initialize multi host bridge, if system support it. Setup ECC options before memory clearing. REDIRECTION causes corrected data to written to RAM immediately. CHIPKILL provides 4 bit error det/corr of x4 type memory. Enable PCI-X clock lines in the AMD controller.

20

Relocate all the CPUs to a unique SMBASE address. The BSP will be set to have its entry point at A000:0. If less than 5 CPU sockets are present on a board, subsequent CPUs entry points will be separated by 8000h bytes. If more than 4 CPU sockets are present, entry points are separated by 200h bytes. CPU module will be responsible for the relocation of the CPU to correct address. NOTE: APs are left in the INIT state.

24

Uncompress and initialize any platform specific BIOS modules.

30

Initialize System Management Interrupt.

2A

Initializes different devices through DIM.

2C

Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.

2E

Initializes all the output devices.

31

Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.

33

Initializes the silent boot module. Set the window for displaying text information.

37

Displaying sign-on message, CPU information, setup key message, and any OEM specific information.

38

Initializes different devices through DIM.

39

Initializes DMAC-1 and DMAC-2.

3A

Initialize RTC date/time.

3B

Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.

3C

By this point, RAM read/write test is completed, program memory holes or handle any adjustments needed in RAM size with respect to NB. Test if HT Module found an error in BootBlock and CPU compatibility for MP environment.

40

Detect different devices (Parallel ports, serial ports, and coprocessor in CPU,... etc.) successfully installed in the system and update the BDA, EBDA,... etc.

50

Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.

52

Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.

60

Initializes NUM-LOCK status and programs the KBD typematic rate.

75

Initialize Int-13 and prepare for IPL detection.

78

Initializes IPL devices controlled by BIOS and option ROMs.

7A

Initializes remaining option ROMs.

7C

Generate and write contents of ESCD in NVRam.

84

Log errors encountered during POST.

85

Display errors to the user and gets the user response for error.

87

Execute BIOS setup if needed/requested.

8C

After all device initialization is done, programmed any user selectable parameters relating to NB/SB, such as timing parameters, non-cacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node.

8D

Build ACPI tables (if ACPI is supported).

8E

Program the peripheral parameters. Enable/Disable NMI as selected.

90

Late POST initialization of system management interrupt.

A0

Check boot password if installed.

A1

Clean-up work needed before booting to OS.

A2

Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.

A4

Initialize runtime language module.

A7

Displays the system configuration screen if enabled. Initialize the CPUs before boot, which includes the programming of the MTRRs.

A8

Prepare CPU for OS boot including final MTRR values.

A9

Wait for user input at config display if needed.

AA

Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.

AB

Prepare BBS for Int 19 boot.

AC

Any kind of Chipsets (NB/SB) specific programming needed during End- POST, just before giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming needed during End-POST. Copy OEM specific data from POST_DSEG to RUN_CSEG.

B1

Save system context for ACPI.

00

Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLIHLT state.

61-70

OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may be different from one platform to the next.