BIOS POST Codes

A P P E N D I X B

BIOS POST Codes

Note - The information in this appendix applies to all Sun Fire X4100/X4100 M2 and X4200/X4200 M2 servers, unless otherwise noted in the text.

The system BIOS provides a rudimentary power-on self-test. The basic devices required for the server to operate are checked, memory is tested, the LSI 1064 disk controller and attached disks are probed and enumerated, and the two Intel dual-Gigabit Ethernet controllers are initialized.

The progress of the self-test is indicated by a series of POST codes.

These codes are displayed at the bottom right corner of the system’s VGA screen (once the self-test has progressed far enough to initialize the video monitor). However, the codes are displayed as the self-test runs and scroll off of the screen too quickly to be read. An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Redirecting Console Output).

The message, BMC Responding, is displayed at the end of POST.

B.1 How BIOS POST Memory Testing Works

The BIOS POST memory testing is performed as follows:

1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is shadowed (that is, copied from ROM to DRAM).

2. Once executing out of DRAM, the BIOS performs a simple memory test (a write/read of every location with the pattern 55aa55aa).

Note - This memory test is performed only if Quick Boot is not enabled from the Boot Settings Configuration screen. Enabling Quick Boot causes the BIOS to skip the memory test. See Changing POST Options for more information.

3. The BIOS polls the memory controllers for both correctable and uncorrectable memory errors and logs those errors into the service processor.

B.2 Redirecting Console Output

Use this procedure to access the service processor and redirect the console output so that the BIOS POST codes can be read.

1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

2. The BIOS Main Menu screen is displayed. Select Advanced.

3. The Advanced Settings screen is displayed. Select IPMI 2.0 Configuration.

4. The IPMI 2.0 Configuration screen is displayed. Select the LAN Configuration menu item.

5. Select the IP Address menu item.

The service processor’s IP address is displayed using the following format:
Current IP address in BMC: xxx.xxx.xxx.xxx

6. Start a web browser and type the service processor’s IP address in the browser’s URL field.

7. When you are prompted, type a user name and password as follows:

User name: rootPassword: changeme

8. When the ILOM Service Processor GUI screen is displayed, click the Remote Control tab.

9. Click the Redirection tab.

10. Set the color depth for the redirection console at either 6 or 8 bits.

11. Click the Start Redirection button.

The javaRConsole window is displayed and prompts you for your user name and password again.

12. When you are prompted, type a user name and password as follows:

User name: rootPassword: changeme

The current POST screen is displayed.

B.3 Changing POST Options

This procedure is optional, but you can use it to change the operations that the server performs during POST testing.

1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

2. The BIOS Main Menu screen is displayed. Select the Boot menu.

3. The Boot Settings screen. Select Boot Settings Configuration.

4. The Boot Settings Configuration screen appears. There are several options that you can enable or disable:

Quick Boot: This option is disabled by default. If you enable this, the BIOS skips certain tests while booting, such as the extensive memory test. This decreases the time it takes for the system to boot.

System Configuration Display: This option is disabled by default. If you enable this, the system configuration screen is displayed before booting begins.

Quiet Boot: This option is disabled by default. If you enable this, the Sun Microsystems logo is displayed instead of POST codes.

Language: This option is reserved for future use. Do not change.

Add On ROM Display Mode: This option is set to Force BIOS by default. This option has effect only if you have also enabled the Quiet Boot option, but it controls whether output from the Option ROM is displayed. The two settings for this option are as follows:

Force BIOS: Remove the Sun logo and display Option ROM output.

Keep Current: Do not remove the Sun logo. The Option ROM output is not displayed.

Boot Num-Lock: This option is On by default (keyboard Num-Lock is turned on during boot). If you set this to off, the keyboard Num-Lock is not turned on during boot.

Wait for F1 if Error: This option is disabled by default. If you enable this, the system will pause if an error is found during POST and will only resume when you press the F1 key.

Interrupt 19 Capture: This option is reserved for future use. Do not change.

Default Boot Order: The letters in the brackets represent the boot devices. To see the letters defined, position your cursor over the field and read the definition in the right side of the screen.

B.4 POST Codes

TABLE B-1 describes each of the POST codes, listed in the same order in which they are generated. These POST codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST codes listed in TABLE B-1, the first two digits are from port 81 and the last two digits are from port 80.

TABLE B-1 POST Codes
Post Code	Description
00d0	Comes out of POR, initializes PCI configuration space, enables 8111’s SMBus.
00d1	Keyboard controller BAT, wakes up from PM, saves power-on CPUID in scratch CMOS.
00d2	Disables cache, full memory sizing, verifies that flat mode is enabled.
00d3	Detects memory and sizing in boot block, disables cache, enables IO APIC.
01d4	Tests base 512KB memory. Adjusts policies and caches first 8MB.
01d5	Copies boot block code from ROM to lower RAM. BIOS now executes out of RAM.
01d6	Determines via key sequence and OEM-specific method if BIOS recovery is forced. If next code is E0, BIOS recovery executes. Tests main BIOS checksum.
01d7	Restores CPUID, moves boot block runtime interface module to RAM, determines whether to execute serial flash.
01d8	Decompresses runtime module into RAM. Stores CPUID information in memory.
01d9	Copies main BIOS into memory.
01da	Gives control to BIOS POST.
0004	Check the CMOS diagnostic byte to determine if battery power is OK and the CMOS checksum is OK. If the CMOS checksum is bad, updates the CMOS with power-on default values.
00c2	Sets up the boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for the GART Error Reporting setup question.
00c3	Applies errata workarounds to the BSP (#78 & #110).
00c6	Re-enables cache for boot strap processor, and applies workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate.
00c7	The HT sets link frequencies and widths to their final values.
000a	Initializes the 8042-compatible keyboard controller.
000c	Detects the presence of a keyboard in the KBC port.
000e	Tests and initializes different input devices. Traps the INT09h vector so that the POST INT09h handler gets control for IRQ1.
8600	Prepares the CPU for booting to the OS by copying all of the context of the BSP to all application processors present. APs are left in the CLI HLT state.
de00	Prepares the CPU for booting to the OS by copying all of the context of the BSP to all application processors present. APs are left in the CLI HLT state.
8613	Initializes PM regs and PM PCI regs at early POST. Initializes the multihost bridge, if the system supports it. Sets up ECC options before memory clearing. Enables PCI-X clock lines in the 8131.
0024	Decompresses and initializes any platform-specific BIOS modules.
862a	Inititalizes BBS ROM.
002a	Generic Device Initialization Manager (DIM) - Disables all devices.
042a	ISA PnP devices - Disables all devices.
052a	PCI devices - Disables all devices.
122a	ISA devices - Static device initialization.
152a	PCI devices - Static device initialization.
252a	PCI devices - Output device initialization.
202c	Initializes different devices. Detects and initializes the video adapter installed in systems that have optional ROMs.
002e	Initializes all the output devices.
0033	Initializes the silent boot module. Sets the window for displaying text information.
0037	Displays sign-on message, CPU information, setup key message, and any OEM-specific information.
4538	PCI devices - IPL device initialization.
5538	PCI devices - General device initialization.
8600	Prepares the CPU for booting to the OS by copying all of the context of the BSP to all application processors present. APs are left in the CLI HLT state.

B.5 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. TABLE B-2 describes the type of checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80.

TABLE B-2 POST Code Checkpoints
Post Code	Description
03	Disables the NMI, parity, video for the EGA, and the DMA controllers. At this point, only ROM accesses are to the GPNV. If the BB size is 64K, requires turning on ROM decode below FFFF0000h. It should allow the USB to run in the E000 segment. Though the HT must program the NB-specific initialization, it can also program the OEM-specific initialization if needed at the beginning of BIOS POST, for instance to override default kernel variables.
04	Checks the CMOS diagnostic byte to determine if battery power is OK and the CMOS checksum is OK. Verifies the CMOS checksum manually by reading storage area. If the CMOS checksum is bad, updates the CMOS with power-on default values and clears passwords. Initializes status register A. Initializes data variables based on the CMOS setup questions. Initializes both 8259-compatible PICs in the system.
05	Initializes the interrupt controlling hardware (generally PIC) and the interrupt vector table.
06	Performs R/W test to the CH-2 count reg. Initializes CH-0 as the system timer. Installs the POSTINT1Ch handler. Enables IRQ-0 in the PIC for system timer interrupt. Traps the INT1Ch vector to POSTINT1ChHandlerBlock.
C0	Starts early CPU initialization, disables Cache, initializes local APIC.
C1	Sets up the boot strap processor information.
C2	Sets up the boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for the GART Error Reporting setup question.
C3	Applies errata workarounds to the BSP (#78 & #110).
C5	Enumerates and sets up application processors. This includes microcode loading and workarounds for errata (#78, #110, #106, #107, #69, #63).
C6	Re-enables cache for boot strap processor, and applies workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. APs are left in the CLI HLT state.
C7	The HT sets link frequencies and widths to their final values. This routine is called after CPU frequency has been calculated to prevent bad programming.
0A	Initializes the 8042-compatible Keyboard Controller.
0B	Detects the presence of a PS/2 mouse.
0C	Detects the presence of a keyboard in the KBC port.
0E	Tests and initializes different input devices. Also updates kernel variables. Traps the INT09h vector so that the POST INT09h handler gets control for IRQ1. Decompresses all available language, BIOS logo, and silent logo modules.
13	Initializes PM regs and PM PCI regs at early POST. Initializes multi host bridge if the system supports it. Sets up ECC options before memory clearing. REDIRECTION causes corrected data to be written to RAM immediately. CHIPKILL provides 4 bit error det/corr of x4 type memory. Enables PCI-X clock lines in the 8131.
20	Relocates all CPUs to a unique SMBASE address. Sets the BSP to have its entry point at A000:0. If less than 5 CPU sockets are present on a board, subsequent CPU entry points are separated by 8000h bytes. If more than four CPU sockets are present, entry points are separated by 200h bytes. The CPU module relocates the CPU to the correct address. APs are left in the INIT state.
24	Decompresses and initializes any platform-specific BIOS modules.
30	Initializes System Management Interrupt.
2A	Initializes different devices through DIM.
2C	Initializes different devices. Detects and initializes the video adapter installed in systems that have optional ROMs.
2E	Initializes all the output devices.
31	Allocates memory for the ADM module and decompresses it. Gives control to the ADM module for initialization. Initializes language and font modules for the ADM. Activates the ADM module.
33	Initializes the silent boot module. Sets the window for displaying text information.
37	Displays sign-on message, CPU information, setup key message, and any OEM-specific information.
38	Initializes different devices through the DIM.
39	Initializes DMAC-1 and DMAC-2.
3A	Initializes RTC date/time.
3B	Tests for total memory installed in the system. Also checks for DEL or ESC keys to limit memory test. Displays total memory in the system.
3C	Signals that the RAM read/write test is completed, and programs memory holes or handles any adjustments needed in RAM size for the NB. Tests if the HT module found an error in the boot block and for CPU compatibility with the MP environment.
40	Detects different devices (parallel ports, serial ports, and the coprocessor in the CPU, etc.) that are successfully installed in the system and updates the BDA, EBDA and so on.
50	Programs the memory hole or any implementation that needs an adjustment in system RAM size.
52	Updates the CMOS memory size from memory found in the memory test. Allocates memory for the Extended BIOS Data Area from base memory.
60	Initializes NUM-LOCK status and programs the KBD typematic rate.
75	Initializes Int-13 and prepares for IPL detection.
78	Initializes IPL devices controlled by BIOS and option ROMs.
7A	Initializes remaining option ROMs.
7C	Generates and writes the contents of ESCD in NVRam.
84	Logs errors encountered during POST.
85	Displays errors to the user and gets the user’s response
87	Executes BIOS setup if needed/requested.
8C	After completing all device initialization, programs any user selectable parameters relating to the NB/SB, such as timing parameters, noncacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCIX/OEM-specific programming needed during late POST. Initiates background scrubbing for the DRAM, and sets up L1 and L2 caches based on setup questions. Gets the DRAM scrub limits from each node. Applies workarounds for erratum #101.
8D	Builds ACPI tables (if ACPI is supported).
8E	Programs the peripheral parameters. Enables/disables the NMI as selected.
90	Initializes late POST system management interrupt.
A0	Checks boot password if installed.
A1	Cleans-up work necessary before booting to OS.
A2	Prepares the runtime image for different BIOS modules. Fills the free area in the F000h segment with 0FFh. Initializes the Microsoft IRQ routing table. Prepares the runtime language module. Disables the system configuration display if needed.
A4	Initializes the runtime language module.
A7	Displays the system configuration screen if enabled. Initializes the CPUs before boot, which includes the programming of the MTRRs.
A8	Prepares the CPU for OS boot including final MTRR values.
A9	Waits for user input at the config display, if needed.
AA	Uninstalls the POST INT1Ch vector and the INT09h vector. Deinitializes the ADM module.
AB	Prepares the BBS for Int 19 boot.
AC	Indicates chipset-specific (NB/SB) programming needed during end POST, just before giving control to runtime code booting to the OS. Programs the system BIOS (0F0000h shadow RAM) cacheability. Ports to handle any OEM-specific programming needed during end POST. Copies OEM-specific data from POST_DSEG to RUN_CSEG.
B1	Saves system context for the ACPI.
00	Prepares the CPU for booting to the OS by copying all of the context of the BSP to all application processors present. APs are left in the CLIHLT state.
61-70	Indicates OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may differ among platforms