CFh

Test CMOS R/W functionality.

C0h

Early chipset initialization:

• Disable shadow RAM.
• Disable L2 cache (socket 7 or below).
• Program basic chipset registers.

C1h

Detect memory:

• Auto-detection of DRAM size, type, and ECC.
• Auto-detection of L2 cache (socket 7 or below).

C3h

Expand compressed BIOS code to DRAM.

C5h

Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.

01h

Expand the Xgroup codes locating in physical address 1000:0.

02h

Reserved.

03h

Initial Superio_Early_Init switch.

04h

Reserved.

05h

1. Blank out screen.

2. Clear CMOS error flag.

06h

Reserved.

07h

1. Clear 8042 interface.

2. Initialize 8042 self-test.

08h

1. Test special keyboard controller for Winbond 977 series Super I/O chips.

2. Enable keyboard interface.

09h

Reserved.

0Ah

1. Disable PS/2 mouse interface (optional).

2. Auto-detect ports for keyboard and mouse followed by a port and interface swap (optional).

3. Reset keyboard for Winbond 977 series Super I/O chips.

0Bh

Reserved.

0Ch

Reserved.

0Dh

Reserved.

0Eh

Test F000h segment shadow to see whether it is read/write-able or not. If test fails, keep beeping the speaker.

0Fh

Reserved.

10h

Auto-detect flash type to load appropriate flash R/W codes into the run -time area in F000 for ESCD & DMI support.

11h

Reserved.

12h

Use walking 1's algorithm to check out interface in CMOS circuitry. Also, set real-time clock power status, and then check for override.

13h

Reserved.

14h

Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers.

15h

Reserved.

16h

Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26h.

17h

Reserved.

18h

Detect CPU information including brand, SMI type (Cyrix or Intel), and CPU level (586 or 686).

19h

Reserved.

1Ah

Reserved.

1Bh

Initial interrupts vector table. If no special specified, all hardware interrupts are directed to SPURIOUS_INT_HDLR and software interrupts to SPURIOUS_soft_HDLR.

1Ch

Reserved.

1Dh

Initial EARLY_PM_INIT switch.

1Eh

Reserved.

1Fh

Load keyboard matrix (notebook platform).

20h

Reserved.

21h

HPM initialization (notebook platform).

22h

Reserved.

23h

1. Check validity of RTC value-e.g. a value of 5Ah is an invalid value for RTC minute.

2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.

24h

Prepare BIOS resource map for PCI and PnP use. If ESCD is valid, consider the ESCD's legacy information.

25h

Early PCI initialization:

• Enumerate PCI bus number.
• Assign memory and I/O resource.
• Search for a valid VGA device and VGA BIOS, and put it into C000:0.

26h

1. If Early_Init_Onboard_Generator is not defined, Onboard clock generator initialization. Disable respective clock resource to empty PCI and DIMM slots.

2. Init onboard PWM.

3. Init onboard H/W monitor devices.

27h

Initialize INT 09 buffer.

28h

Reserved.

29h

1. Program CPU internal MTRR (P6 and PII) for 0-640K memory address.

2. Initialize the APIC for Pentium class CPU.

3. Program early chipset according to CMOS setup. Example: onboard IDE controller.

4. Measure CPU speed.

2Ah

Reserved.

2Bh

Invoke video BIOS.

2Ch

Reserved.

2Dh

1. Initialize double-byte language font (optional).

2. Put information onscreen display, including award title, CPU type, CPU speed, and full screen logo.

2Eh

Reserved.

2Fh

Reserved.

30h

Reserved.

31h

Reserved.

32h

Reserved.

33h

Reset keyboard if Early_Reset_KB is defined-e.g. Winbond 977 series Super I/O chips. See also POST 63h.

34h

Reserved.

35h

Test DMA Channel 0.

36h

Reserved.

37h

Test DMA Channel 1.

38h

Reserved.

39h

Test DMA page registers.

3Ah

Reserved.

3Bh

Reserved.

3Ch

Test 8254.

3Dh

Reserved.

3Eh

Test 8259 interrupt mask bits for channel 1.

3Fh

Reserved.

40h

Test 8259 interrupt mask bits for channel 2.

41h

Reserved.

42h

Reserved.

43h

Test 8259 functionality.

44h

Reserved.

45h

Reserved.

46h

Reserved.

47h

Initialize EISA slot.

48h

Reserved.

49h

1. Calculate total memory by testing the last double word of each 64K page.

2. Program-write allocation for AMD K5 CPU.

4Ah

Reserved.

4Bh

Reserved.

4Ch

Reserved.

4Dh

Reserved.

4Eh

1. Program MTRR of M1 CPU.

2. Initialize L2 cache for P6 class CPU and program CPU with proper cacheable range.

3. Initialize the APIC for P6 class CPU.

4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical.

4Fh

Reserved.

50h

Initialize USB keyboard and mouse.

51h

Reserved.

52h

Test all memory (clear all extended memory to 0).

53h

Clear password according to H/W jumper (optional).

54h

Reserved.

55h

Display number of processors (multiprocessor platform).

56h

Reserved.

57h

1. Display PnP logo.

2. Early ISA PnP initialization. Assign CSN to every ISA PnP device.

58h

Reserved.

59h

Initialize the combined Trend Anti-Virus code.

5Ah

Reserved.

5Bh

(Optional feature) Show message for entering AWDFLASH.EXE from FDD.

5Ch

Reserved.

5Dh

1. Initialize Init_Onboard_Super_IO.

2. Initialize Init_Onbaord_AUDIO.

5Eh

Reserved.

5Fh

Reserved.

60h

Okay to enter setup utility; users cannot enter the CMOS setup utility until this POST stage.

61h

Reserved.

62h

Reserved.

63h

Reset keyboard if Early_Reset_KB is not defined.

64h

Reserved.

65h

Initialize PS/2 Mouse.

66h

Reserved.

67h

Prepare memory size information for function call: INT 15h ax=E820h.

68h

Reserved.

69h

Turn on L2 cache.

6Ah

Reserved.

6Bh

Program chipset registers according to items described in Setup & Auto-configuration table.

6Ch

Reserved.

6Dh

1. Assign resources to all ISA PnP devices.

2. Auto assign ports to onboard COM ports if the corresponding item in Setup is set to AUTO.

6Eh

Reserved.

6Fh

1. Initialize diskette controller.

2. Set up diskette-related fields in 40:hardware.

70h

Reserved.

71h

Reserved.

72h

Reserved.

73h

Reserved.

74h

Reserved.

75h

Detect and install all IDE devices: HDD, LS120, ZIP, CDROM....

76h

(Optional Feature) Enter AWDFLASH.EXE if:

• AWDFLASH.EXE is found on diskette drive.
• ALT+F2 is pressed.

77h

Detect serial ports and parallel ports.

78h

Reserved.

79h

Reserved.

7Ah

Detect and install co-processor.

7Bh

Reserved.

7Ch

Init HDD write-protect.

7Dh

Reserved.

7Eh

Reserved.

7Fh

Switch back to text mode if full-screen logo is supported.

• If errors occur, report errors and wait for keys.
• If no errors occur or you press the F1 key to continue: Clear EPA or customization logo.

80h

Reserved.

81h

Reserved.

E8POST.ASM starts.

82h

1. Call chipset power management hook.

2. Recover the text fond used by EPA logo (not for full screen logo).

3. If password is set, ask for password.

83h

Save all data in stack back to CMOS.

84h

Initialize ISA PnP boot devices.

85h

1. USB final initialization.

2. Switch screen back to text mode.

86h

Reserved.

87h

NET PC: Build SYSID Structure.

88h

Reserved.

89h

1. Assign IRQs to PCI devices.

2. Set up ACPI table at top of the memory.

8Ah

Reserved.

8Bh

1. Invoke all ISA adapter ROMs.

2. Invoke all PCI ROMs (except VGA).

8Ch

Reserved.

8Dh

1. Enable/disable parity check according to CMOS setup.

2. APM initialization.

8Eh

Reserved.

8Fh

Clear noise of IRQs.

90h

Reserved.

91h

Reserved.

92h

Reserved.

93h

Read HDD boot sector information for Trend Anti-Virus code.

94h

1. Enable L2 cache.

2. Program Daylight Saving.

3. Program boot-up speed.

4. Chipset final initialization.

5. Power management final initialization.

6. Clear screen and display summary table.

7. Program K6 write allocation.

8. Program P6 class write combining.

95h

Update keyboard LED and typematic rate.

96h

1. Build MP table.

2. Build and update ESCD.

3. Set CMOS century to 20h or 19h.

4. Load CMOS time into DOS timer tick.

5. Build MSIRQ routing table.

FFh

Boot attempt (INT 19h).