3.1.1 The Makefile

A file called makefile tells make in a structured manner which source and object files depend on other files. It also defines the commands required to compile and link the files.

For example, suppose you have a program of four source files and the makefile:

demo% ls
makefile
commonblock
computepts.f
pattern.f
startupcore.f
demo%

Assume both pattern.f and computepts.f have an INCLUDE of commonblock, and you wish to compile each.f file and link the three relocatable files, along with a series of libraries, into a program called pattern.

The makefile looks like this:

demo% cat makefile
pattern: pattern.o computepts.o startupcore.o
      f95 pattern.o computepts.o startupcore.o -lcore95 \
      -lcore -lsunwindow -lpixrect -o pattern
pattern.o: pattern.f commonblock
      f95 -c -u pattern.f
computepts.o: computepts.f commonblock
      f95 -c -u computepts.f
startupcore.o: startupcore.f
      f95 -c -u startupcore.f
demo%

The first line of makefile indicates that making pattern depends on pattern.o, computepts.o, and startupcore.o. The next line and its continuations give the command for making pattern from the relocatable.o files and libraries.

Each entry in makefile is a rule expressing a target object’s dependencies and the commands needed to make that object. The structure of a rule is:

target: dependencies-listTAB build-commands

• Dependencies. Each entry starts with a line that names the target file, followed by all the files the target depends on.

• Commands. Each entry has one or more subsequent lines that specify the Bourne shell commands that will build the target file for this entry. Each of these command lines must be indented by a tab character.