The make utility’s macro facility allows simple, parameterless string substitutions. For example, the list of relocatable files that make up the target program pattern can be expressed as a single macro string, making it easier to change.
A macro string definition has the form:
NAME = string
Use of a macro string is indicated by:
$(NAME)
which is replaced by make with the actual value of the macro string.
This example adds a macro definition naming all the object files to the beginning of makefile:
OBJ = pattern.o computepts.o startupcore.o |
Now the macro can be used in both the list of dependencies as well as on the f95 link command for target pattern in makefile:
pattern: $(OBJ) f95 $(OBJ) -lcore95 -lcore -lsunwindow \ -lpixrect -o pattern |
For macro strings with single-letter names, the parentheses may be omitted.