SPARC Assembly Language Reference Manual

E.6.6 Graphics Instructions

Unless otherwise specified, floating-point registers contain all instruction operands. There are 32 double-precision registers. Single-precision floating-point registers contain the pixel values, and double-precision floating-point registers contain the fixed values.

The opcode space reserved for the Implementation-Dependent Instruction1 (IMPDEP1) instructions is where the graphics instruction set is mapped.

Partitioned add/subtract instructions perform two 32-bit or four 16-bit partitioned adds or subtracts between the source operands corresponding fixed point values.

Table E–15


SPARC	Mnemonic	Argument List	Description
`FPADD16` `FPADD16S` `FPADD32` `FPADD32S` `FPSUB16` `FPSUB16S` `FPSUB32` `FPSUB32S`	`fpadd16` `fpadd16s` `fpadd32` `fpadd32s` `fpsub16` `fpsub16s` `fpsub32` `fpsub32s`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	four 16-bit add two 16-bit add two 32-bit add one 32-bit add four 16-bit subtract two 16-bit subtract two 32-bit subtract one 32-bit subtract

Pack instructions convert to a lower pixel or precision fixed format.

Table E–16


SPARC	Mnemonic	Argument List	Description
`FPACK16` `FPACK32` `FPACKFIX` `FEXPAND` `FPMERGE`	`fpack16` `fpack32` `fpackfix` `fexpand` `fpmerge`	freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs2, freg_rd freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	four 16-bit packs two 32-bit packs four 16-bit packs four 16-bit expands two 32-bit merges

Partitioned multiply instructions have the following variations.

Table E–17


SPARC	Mnemonic	Argument List	Description
`FMUL8x16` `FMUL8x16AU` `FMUL8x16AL` `FMUL8SUx16` `FMUL8ULx16` `FMULD8SUx16` `FMULD8ULx16`	`fmul8x16` `fmul8x16au` `fmul8x16al` `fmul8sux16` `fmul8ulx16` `fmuld8sux16` `fmuld8ulx16`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	8x16-bit partition 8x16-bit upper partition 8x16-bit lower partition upper 8x16-bit partition lower unsigned 8x16-bit partition upper 8x16-bit partition lower unsigned 8x16-bit partition

Alignment instructions have the following variations.

Table E–18


SPARC	Mnemonic	Argument List	Description
`ALIGNADDRESS` `ALIGNADDRESS_LITTLE` `FALIGNDATA`	`alignaddr` `alignaddrl` `faligndata`	reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd freg_rs1, freg_rs2, freg_rd	find misaligned data access address same as above, but little-endian do misaligned data, data alignment

Logical operate instructions perform one of sixteen 64-bit logical operations between rs1 and rs2 (in the standard 64-bit version).

Table E–19


SPARC	Mnemonic	Argument List	Description
`FZERO` `FZEROS` `FONE` `FONES` `FSRC1`	`fzero` `fzeros` `fone` `fones` `fsrc1`	`freg_rd` `freg_rd` `freg_rd` `freg_rd` `freg_rs1`, `freg_rd`	zero fill zero fill, single precision one fill one fill, single precision copy src1
`FSRC1S` `FSRC2` `FSRC2S` `FNOT1` `FNOT1S`	`fsrc1s` `fsrc2` `fsrc2s` `fnot1` `fnot1s`	freg_rs1, freg_rd freg_rs2, freg_rd freg_rs2, freg_rd freg_rs1, freg_rd freg_rs1, freg_rd	copy src1, single precision copy src2 copy src2, single precision negate src1, 1's complement same as above, single precision
`FNOT2` `FNOT2S` `FOR` `FORS` `FNOR`	`fnot2` `fnot2s` `for` `fors` `fnor`	freg_rs2, freg_rd freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	negate src2, 1's complement same as above, single precision logical OR logical OR, single precision logical NOR
`FNORS` `FAND` `FANDS` `FNAND` `FNANDS`	`fnors` `fand` `fands` `fnand` `fnands`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	logical NOR, single precision logical AND logical AND, single precision logical NAND logical NAND, single precision
`FXOR` `FXORS` `FXNOR` `FXNORS` `FORNOT1`	`fxor` `fxors` `fxnor` `fxnors` `fornot1`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	logical XOR logical XOR, single precision logical XNOR logical XNOR, single precision negated src1 OR src2
`FORNOT1S` `FORNOT2` `FORNOT2S` `FANDNOT1`	`fornot1s` `fornot2` `fornot2s` `fandnot1`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	same as above, single precision src1 OR negated src2 same as above, single precision negated src1 AND src2
`FANDNOT1S` `FANDNOT2` `FANDNOT2S`	`fandnot1s` `fandnot2` `fandnot2s`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	same as above, single precision src1 AND negated src2 same as above, single precision

Pixel compare instructions compare fixed-point values in rs1 and rs2 (two 32 bit or four 16 bit)

Table E–20


SPARC	Mnemonic	Argument List	Description
`FCMPGT16` `FCMPGT32` `FCMPLE16` `FCMPLE32`	`fcmpgt16` `fcmpgt32` `fcmple16` `fcmple32`	freg_rs1, freg_rs2, reg_rd freg_rs1, freg_rs2, reg_rd freg_rs1, freg_rs2, reg_rd freg_rs1, freg_rs2, reg_rd	4 16-bit compare, set rd if src1>src2 2 32-bit compare, set rd if src1>src2 4 16-bit compare, set rd if src1≤src2 2 32-bit compare, set rd if src1≤src2
`FCMPNE16` `FCMPNE32` `FCMPEQ16` `FCMPEQ32`	`fcmpne16` `fcmpne32` `fcmpeq16` `fcmpeq32`	freg_rs1, freg_rs2, reg_rd freg_rs1, freg_rs2, reg_rd freg_rs1, freg_rs2, reg_rd freg_rs1, freg_rs2, reg_rd	4 16-bit compare, set rd if src1≠src2 2 32-bit compare, set rd if src1≠src2 4 16-bit compare, set rd if src1=src2 2 32-bit compare, set rd if src1=src2

Edge handling instructions handle the boundary conditions for parallel pixel scan line loops.

Table E–21


SPARC	Mnemonic	Argument List	Description
`EDGE8` `EDGE8L` `EDGE16`	`edge8` `edge8l` `edge16`	reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd	8 8-bit edge boundary processing same as above, little-endian 4 16-bit edge boundary processing
`EDGE16L` `EDGE32` `EDGE32L`	`edge16l` `edge32` `edge32l`	reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd	same as above, little-endian 2 32-bit edge boundary processing same as above, little-endian

Pixel component distance instructions are used for motion estimation in video compression algorithms.

Table E–22


SPARC	Mnemonic	Argument List	Description
`PDIST`	`pdist`	freg_rs1, freg_rs2, freg_rd	8 8-bit components, distance between

The three-dimensional array addressing instructions convert three- dimensional fixed-point addresses (in rs1) to a blocked-byte address. The result is stored in rd.

Table E–23


SPARC	Mnemonic	Argument List	Description
`ARRAY8` `ARRAY16` `ARRAY32`	`array8` `array16` `array32`	reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd reg_rs1, reg_rs2, reg_rd	convert 8-bit 3-D address to blocked byte address same as above, but 16-bit same as above, but 32-bit