SPARC Assembly Language Reference Manual

E.5 SPARC-V9 Synthetic Instruction-Set Mapping

Here is a mapping of synthetic instructions to hardware equivalent instructions.

Table E–12


Synthetic Instruction		Hardware Equivalent(s)		Comment
`cas` `casl` `casx` `casxl`	[reg_rsl], reg_rs2, reg_rd [reg_rsl], reg_rs2, reg_rd [reg_rsl], reg_rs2, reg_rd [reg_rsl], reg_rs2, reg_rd	`casa` `casa` `casxa` `casxa`	[reg_rsl]ASI_P, reg_rs2, reg_rd [reg_rsl]ASI_P_L, reg_rs2, reg_rd [reg_rsl]ASI_P, reg_rs2, reg_rd [reg_rsl]ASI_P_L, reg_rs2, reg_rd	Compare & swap (cas) cas little-endian cas extended cas little-endian, extended
`clrx`	[address]	`stx`	`%g0`, [address]	Clear extended word
`clruw` `clruw`	reg_rs1, reg_rd reg_rd	`srl` `srl`	reg_rs1, %g0, reg_rd reg_rd, %g0, reg_rd	Copy and clear upper word Clear upper word
`iprefetch`	label	`bn`, `pt`	%xcc, label	Instruction prefetch,
`mov` `mov` `mov`	%y, reg_rd %asrn, reg_rd reg_or_imm, %asrn	`rd` `rd` `wr`	%y, reg_rd %asrn, reg_rd %g0, reg_or_imm, %asrn
`ret` `retl`		`jmpl` `jmpl`	%i7+8, %g0 %o7+8, %g0	Return from subroutine Return from leaf subroutine
`setn`	value, r1, r2	for `-xarch=v9` same as `setx` value r1, r2 for `-xarch=v8` same as `set` value r2
`setnhi`	value, r1, r2	for `-xarch=v9` same as `setxhi` value r1, r2 for `-xarch=v8` same as `sethi` value r2
`setuw`	value,reg_rd	`sethi` `or` `sethi` `or`	`%hi`(value), reg_rd `%g0`, value, reg_rd `%hi`(value), reg_rd; reg_rd, `%lo`(value), reg_rd	(value & 3FF₁₆)==0 when 0 ≤ value `≤` 4095 (otherwise) Do not use setuw in a DCTI delay slot.
`setsw`	value,reg_rd	`sethi` `or` `sethi` `sra` `sethi` `or` `sethi` `or` `sra`	`%hi`(value), reg_rd `%g0`, value, reg_rd `%hi`(value), reg_rd reg_rd, `%g0`, reg_rd `%hi`(value), reg_rd; reg_rd, `%lo`(value), reg_rd `%hi`(value), reg_rd; reg_rd, `%lo`(value), reg_rd reg_rd, `%g0`, reg_rd	value>=0 and (value & 3FF₁₆)==0 -4096 ≤ value ≤ 4095 if (value<0) and ((value & 3FF)==0) (otherwise, if value>=0) (otherwise, if value<0) Do not use setsw in a CTI delay slot.
`setx`	value, r1, r2	`sethi` `or` `sethi` `or` `sllx` `or`	%hh(value), r1 r1, %hm(value), r1 %lm(value), r2 r2, %lo(value), r2 r1, 32, r1 r1, r2, r2
`setxhi`	value r1, r2	`sethi` `or` `sethi` `sllx` `or`	%hh(value), r1 r1, %hm(value), r1 %lm(value), r2 r1, 32, r1 r1, r2, r2
`signx` `signx`	reg_rsl, reg_rd reg_rd	`sra` `sra`	reg_rsl, %g0, reg_rd reg_rd,%g0, reg_rd	Sign-extend 32-bit value to 64 bits