x86 Assembly Language Reference Manual

General-Purpose Instructions

The general-purpose instructions perform basic data movement, memory addressing, arithmetic and logical operations, program flow control, input/output, and string operations on integer, pointer, and BCD data types.

Data Transfer Instructions

The data transfer instructions move data between memory and the general-purpose and segment registers, and perform operations such as conditional moves, stack access, and data conversion.

Table 3–1 Data Transfer Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

bswap{lq}

BSWAP

byte swap 

bswapq valid only under -xarch=amd64

cbtw

CBW

convert byte to word 

 

cltd

CDQ

convert doubleword to quadword 

%eax -> %edx:%eax

cltq

CDQE

convert doubleword to quadword 

%eax -> %rax

cltq valid only under -xarch=amd64

cmova{wlq}, cmov{wlq}.a

CMOVA

conditional move if above 

cmovaq valid only under -xarch=amd64

cmovae{wlq}, cmov{wlq}.ae

CMOVAE

conditional move if above or equal 

cmovaeq valid only under -xarch=amd64

cmovb{wlq}, cmov{wlq}.b

CMOVB

conditional move if below 

cmovbq valid only under -xarch=amd64

cmovbe{wlq}, cmov{wlq}.be

CMOVBE

conditional move if below or equal 

cmovbeq valid only under -xarch=amd64

cmovc{wlq}, cmov{wlq}.c

CMOVC

conditional move if carry 

cmovcq valid only under -xarch=amd64

cmove{wlq}, cmov{wlq}.e

CMOVE

conditional move if equal 

cmoveq valid only under -xarch=amd64

cmovg{wlq}, cmov{wlq}.g

CMOVG

conditional move if greater 

cmovgq valid only under -xarch=amd64

cmovge{wlq}, cmov{wlq}.ge

CMOVGE

conditional move if greater or equal 

cmovgeq valid only under -xarch=amd64

cmovl{wlq}, cmov{wlq}.l

CMOVL

conditional move if less 

cmovlq valid only under -xarch=amd64

cmovle{wlq}, cmov{wlq}.le

COMVLE

conditional move if less or equal 

cmovleq valid only under -xarch=amd64

cmovna{wlq}, cmov{wlq}.na

CMOVNA

conditional move if not above 

cmovnaq valid only under -xarch=amd64

cmovnae{wlq}, cmov{wlq}.nae

CMOVNAE

conditional move if not above or equal 

cmovnaeq valid only under -xarch=amd64

cmovnb{wlq}, cmov{wlq}.nb

CMOVNB

conditional move if not below 

cmovnbq valid only under -xarch=amd64

cmovnbe{wlq}, cmov{wlq}.nbe

CMOVNBE

conditional move if not below or equal 

cmovnbeq valid only under -xarch=amd64

cmovnc{wlq}, cmov{wlq}.nc

CMOVNC

conditional move if not carry 

cmovncq valid only under -xarch=amd64

cmovne{wlq}, cmov{wlq}.ne

CMOVNE

conditional move if not equal 

cmovneq valid only under -xarch=amd64

cmovng{wlq}, cmov{wlq}.ng

CMOVNG

conditional move if greater 

cmovngq valid only under -xarch=amd64

cmovnge{wlq}, cmov{wlq}.nge

CMOVNGE

conditional move if not greater or equal 

cmovngeq valid only under -xarch=amd64

cmovnl{wlq}, cmov{wlq}.nl

CMOVNL

conditional move if not less 

cmovnlq valid only under -xarch=amd64

cmovnle{wlq}, cmov{wlq}.nle

CMOVNLE

conditional move if not above or equal 

cmovnleq valid only under -xarch=amd64

cmovno{wlq}, cmov{wlq}.no

CMOVNO

conditional move if not overflow 

cmovnoq valid only under -xarch=amd64

cmovnp{wlq}, cmov{wlq}.np

CMOVNP

conditional move if not parity 

cmovnpq valid only under -xarch=amd64

cmovns{wlq}, cmov{wlq}.ns

CMOVNS

conditional move if not sign (non-negative) 

cmovnsq valid only under -xarch=amd64

cmovnz{wlq}, cmov{wlq}.nz

CMOVNZ

conditional move if not zero 

cmovnzq valid only under -xarch=amd64

cmovo{wlq}, cmov{wlq}.o

CMOVO

conditional move if overflow 

cmovoq valid only under -xarch=amd64

cmovp{wlq}, cmov{wlq}.p

CMOVP

conditional move if parity 

cmovpq valid only under -xarch=amd64

cmovpe{wlq}, cmov{wlq}.pe

CMOVPE

conditional move if parity even 

cmovpeq valid only under -xarch=amd64

cmovpo{wlq}, cmov{wlq}.po

CMOVPO

conditional move if parity odd 

cmovpoq valid only under -xarch=amd64

cmovs{wlq}, cmov{wlq}.s

CMOVS

conditional move if sign (negative) 

cmovsq valid only under -xarch=amd64

cmovz{wlq}, cmov{wlq}.z

CMOVZ

conditional move if zero 

cmovzq valid only under -xarch=amd64

cmpxchg{bwlq}

CMPXCHG

compare and exchange 

cmpxchgq valid only under -xarch=amd64

cmpxchg8b

CMPXCHG8B

compare and exchange 8 bytes 

 

cqtd

CQO

convert quadword to octword 

%rax -> %rdx:%rax

cqtd valid only under -xarch=amd64

cqto

CQO

convert quadword to octword 

%rax -> %rdx:%rax

cqto valid only under -xarch=amd64

cwtd

CWD

convert word to doubleword 

%ax -> %dx:%ax

cwtl

CWDE

convert word to doubleword in %eax register

%ax -> %eax

mov{bwlq}

MOV

move data between immediate values, general purpose registers, segment registers, and memory 

movq valid only under -xarch=amd64

movabs{bwlq}

MOVABS

move immediate value to register 

movabs valid only under -xarch=amd64

movabs{bwlq}A

MOVABS

move immediate value to register {AL, AX, GAX, RAX}

movabs valid only under -xarch=amd64

movsb{wlq}, movsw{lq}

MOVSX

move and sign extend 

movsbq and movswq valid only under -xarch=amd64

movzb{wlq}, movzw{lq}

MOVZX

move and zero extend 

movzbq and movzwq valid only under -xarch=amd64

pop{wlq}

POP

pop stack 

popq valid only under -xarch=amd64

popaw

POPA

pop general-purpose registers from stack 

popaw invalid under -xarch=amd64

popal, popa

POPAD

pop general-purpose registers from stack 

invalid under -xarch=amd64

push{wlq}

PUSH

push onto stack 

pushq valid only under -xarch=amd64

pushaw

PUSHA

push general-purpose registers onto stack 

pushaw invalid under -xarch=amd64

pushal, pusha

PUSHAD

push general-purpose registers onto stack 

invalid under -xarch=amd64

xadd{bwlq}

XADD

exchange and add 

xaddq valid only under -xarch=amd64

xchg{bwlq}

XCHG

exchange 

xchgq valid only under -xarch=amd64

xchg{bwlq}A

XCHG

exchange 

xchgqA valid only under -xarch=amd64

Binary Arithmetic Instructions

The binary arithmetic instructions perform basic integer computions on operands in memory or the general-purpose registers.

Table 3–2 Binary Arithmetic Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

adc{bwlq}

ADC

add with carry 

adcq valid only under -xarch=amd64

add{bwlq}

ADD

integer add 

addq valid only under -xarch=amd64

cmp{bwlq}

CMP

compare 

cmpq valid only under -xarch=amd64

dec{bwlq}

DEC

decrement 

decq valid only under -xarch=amd64

div{bwlq}

DIV

divide (unsigned) 

divq valid only under -xarch=amd64

idiv{bwlq}

IDIV

divide (signed) 

idivq valid only under -xarch=amd64

imul{bwlq}

IMUL

multiply (signed) 

imulq valid only under -xarch=amd64

inc{bwlq}

INC

increment 

incq valid only under -xarch=amd64

mul{bwlq}

MUL

multiply (unsigned) 

mulq valid only under -xarch=amd64

neg{bwlq}

NEG

negate 

negq valid only under -xarch=amd64

sbb{bwlq}

SBB

subtract with borrow 

sbbq valid only under -xarch=amd64

sub{bwlq}

SUB

subtract 

subq valid only under -xarch=amd64

Decimal Arithmetic Instructions

The decimal arithmetic instructions perform decimal arithmetic on binary coded decimal (BCD) data.

Table 3–3 Decimal Arithmetic Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

aaa

AAA

ASCII adjust after addition 

invalid under -xarch=amd64

aad

AAD

ASCII adjust before division 

invalid under -xarch=amd64

aam

AAM

ASCII adjust after multiplication 

invalid under -xarch=amd64

aas

AAS

ASCII adjust after subtraction 

invalid under -xarch=amd64

daa

DAA

decimal adjust after addition 

invalid under -xarch=amd64

das

DAS

decimal adjust after subtraction 

invalid under -xarch=amd64

Logical Instructions

The logical instructions perform basic logical operations on their operands.

Table 3–4 Logical Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

and{bwlq}

AND

bitwise logical AND 

andq valid only under -xarch=amd64

not{bwlq}

NOT

bitwise logical NOT 

notq valid only under -xarch=amd64

or{bwlq}

OR

bitwise logical OR 

orq valid only under -xarch=amd64

xor{bwlq}

XOR

bitwise logical exclusive OR 

xorq valid only under -xarch=amd64

Shift and Rotate Instructions

The shift and rotate instructions shift and rotate the bits in their operands.

Table 3–5 Shift and Rotate Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

rcl{bwlq}

RCL

rotate through carry left 

rclq valid only under -xarch=amd64

rcr{bwlq}

RCR

rotate through carry right 

rcrq valid only under -xarch=amd64

rol{bwlq}

ROL

rotate left 

rolq valid only under -xarch=amd64

ror{bwlq}

ROR

rotate right 

rorq valid only under -xarch=amd64

sal{bwlq}

SAL

shift arithmetic left 

salq valid only under -xarch=amd64

sar{bwlq}

SAR

shift arithmetic right 

sarq valid only under -xarch=amd64

shl{bwlq}

SHL

shift logical left 

shlq valid only under -xarch=amd64

shld{bwlq}

SHLD

shift left double 

shldq valid only under -xarch=amd64

shr{bwlq}

SHR

shift logical right 

shrq valid only under -xarch=amd64

shrd{bwlq}

SHRD

shift right double 

shrdq valid only under -xarch=amd64

Bit and Byte Instructions

The bit instructions test and modify individual bits in operands. The byte instructions set the value of a byte operand to indicate the status of flags in the %eflags register.

Table 3–6 Bit and Byte Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

bsf{wlq}

BSF

bit scan forward 

bsfq valid only under -xarch=amd64

bsr{wlq}

BSR

bit scan reverse 

bsrq valid only under -xarch=amd64

bt{wlq}

BT

bit test 

btq valid only under -xarch=amd64

btc{wlq}

BTC

bit test and complement 

btcq valid only under -xarch=amd64

btr{wlq}

BTR

bit test and reset 

btrq valid only under -xarch=amd64

bts{wlq}

BTS

bit test and set 

btsq valid only under -xarch=amd64

seta

SETA

set byte if above 

 

setae

SETAE

set byte if above or equal 

 

setb

SETB

set byte if below 

 

setbe

SETBE

set byte if below or equal 

 

setc

SETC

set byte if carry 

 

sete

SETE

set byte if equal 

 

setg

SETG

set byte if greater 

 

setge

SETGE

set byte if greater or equal 

 

setl

SETL

set byte if less 

 

setle

SETLE

set byte if less or equal 

 

setna

SETNA

set byte if not above 

 

setnae

SETNAE

set byte if not above or equal 

 

setnb

SETNB

set byte if not below 

 

setnbe

SETNBE

set byte if not below or equal 

 

setnc

SETNC

set byte if not carry 

 

setne

SETNE

set byte if not equal 

 

setng

SETNG

set byte if not greater 

 

setnge

SETNGE

set byte if not greater or equal 

 

setnl

SETNL

set byte if not less 

 

setnle

SETNLE

set byte if not less or equal 

 

setno

SETNO

set byte if not overflow 

 

setnp

SETNP

set byte if not parity 

 

setns

SETNS

set byte if not sign (non-negative) 

 

setnz

SETNZ

set byte if not zero 

 

seto

SETO

set byte if overflow 

 

setp

SETP

set byte if parity 

 

setpe

SETPE

set byte if parity even 

 

setpo

SETPO

set byte if parity odd 

 

sets

SETS

set byte if sign (negative) 

 

setz

SETZ

set byte if zero 

 

test{bwlq}

TEST

logical compare 

testq valid only under -xarch=amd64

Control Transfer Instructions

The control transfer instructions control the flow of program execution.

Table 3–7 Control Transfer Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

bound{wl}

BOUND

detect value out of range 

boundw invalid under -xarch=amd64

call

CALL

call procedure 

 

enter

ENTER

high-level procedure entry 

 

int

INT

software interrupt 

 

into

INTO

interrupt on overflow 

invalid under -xarch=amd64

iret

IRET

return from interrupt 

 

ja

JA

jump if above 

 

jae

JAE

jump if above or equal 

 

jb

JB

jump if below 

 

jbe

JBE

jump if below or equal 

 

jc

JC

jump if carry 

 

jcxz

JCXZ

jump register %cx zero

 

je

JE

jump if equal 

 

jecxz

JECXZ

jump register %ecx zero

invalid under -xarch=amd64

jg

JG

jump if greater 

 

jge

JGE

jump if greater or equal 

 

jl

JL

jump if less 

 

jle

JLE

jump if less or equal 

 

jmp

JMP

jump 

 

jnae

JNAE

jump if not above or equal 

 

jnb

JNB

jump if not below 

 

jnbe

JNBE

jump if not below or equal 

 

jnc

JNC

jump if not carry 

 

jne

JNE

jump if not equal 

 

jng

JNG

jump if not greater 

 

jnge

JNGE

jump if not greater or equal 

 

jnl

JNL

jump if not less 

 

jnle

JNLE

jump if not less or equal 

 

jno

JNO

jump if not overflow 

 

jnp

JNP

jump if not parity 

 

jns

JNS

jump if not sign (non-negative) 

 

jnz

JNZ

jump if not zero 

 

jo

JO

jump if overflow 

 

jp

JP

jump if parity 

 

jpe

JPE

jump if parity even 

 

jpo

JPO

jump if parity odd 

 

js

JS

jump if sign (negative) 

 

jz

JZ

jump if zero 

 

lcall

CALL

call far procedure 

valid as indirect only for -xarg=amd64

leave

LEAVE

high-level procedure exit 

 

loop

LOOP

loop with %ecx counter

 

loope

LOOPE

loop with %ecx and equal

 

loopne

LOOPNE

loop with %ecx and not equal

 

loopnz

LOOPNZ

loop with %ecx and not zero

 

loopz

LOOPZ

loop with %ecx and zero

 

lret

RET

return from far procedure 

valid as indirect only for -xarg=amd64

ret

RET

return 

 

String Instructions

The string instructions operate on strings of bytes. Operations include storing strings in memory, loading strings from memory, comparing strings, and scanning strings for substrings.


Note –

The Solaris mnemonics for certain instructions differ slightly from the Intel/AMD mnemonics. Alphabetization of the table below is by the Solaris mnemonic. All string operations default to long (doubleword).


Table 3–8 String Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

cmps{q}

CMPS

compare string 

cmpsq valid only under -xarch=amd64

cmpsb

CMPSB

compare byte string 

 

cmpsl

CMPSD

compare doubleword string 

 

cmpsw

CMPSW

compare word string 

 

lods{q}

LODS

load string 

lodsq valid only under -xarch=amd64

lodsb

LODSB

load byte string 

 

lodsl

LODSD

load doubleword string 

 

lodsw

LODSW

load word string 

 

movs{q}

MOVS

move string 

movsq valid only under -xarch=amd64

movsb

MOVSB

move byte string 

movsb is not movsb{wlq}. See Table 3–1

movsl, smovl

MOVSD

move doubleword string 

 

movsw, smovw

MOVSW

move word string 

movsw is not movsw{lq}. See Table 3–1

rep

REP

repeat while %ecx not zero

 

repnz

REPNE

repeat while not equal 

 

repnz

REPNZ

repeat while not zero 

 

repz

REPE

repeat while equal 

 

repz

REPZ

repeat while zero 

 

scas{q}

SCAS

scan string 

scasq valid only under -xarch=amd64

scasb

SCASB

scan byte string 

 

scasl

SCASD

scan doubleword string 

 

scasw

SCASW

scan word string 

 

stos{q}

STOS

store string 

stosq valid only under -xarch=amd64

stosb

STOSB

store byte string 

 

stosl

STOSD

store doubleword string 

 

stosw

STOSW

store word string 

 

I/O Instructions

The input/output instructions transfer data between the processor's I/O ports, registers, and memory.

Table 3–9 I/O Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

in

IN

read from a port 

 

ins

INS

input string from a port 

 

insb

INSB

input byte string from port 

 

insl

INSD

input doubleword string from port 

 

insw

INSW

input word string from port 

 

out

OUT

write to a port 

 

outs

OUTS

output string to port 

 

outsb

OUTSB

output byte string to port 

 

outsl

OUTSD

output doubleword string to port 

 

outsw

OUTSW

output word string to port 

 

Flag Control (EFLAG) Instructions

The status flag control instructions operate on the bits in the %eflags register.

Table 3–10 Flag Control Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

clc

CLC

clear carry flag 

 

cld

CLD

clear direction flag 

 

cli

CLI

clear interrupt flag 

 

cmc

CMC

complement carry flag 

 

lahf

LAHF

load flags into %ah register

 

popfw

POPF

pop %eflags from stack

 

popf{lq}

POPFL

pop %eflags from stack

popfq valid only under -xarch=amd64

pushfw

PUSHF

push %eflags onto stack

 

pushf{lq}

PUSHFL

push %eflags onto stack

pushfq valid only under -xarch=amd64

sahf

SAHF

store %ah register into flags

 

stc

STC

set carry flag 

 

std

STD

set direction flag 

 

sti

STI

set interrupt flag 

 

Segment Register Instructions

The segment register instructions load far pointers (segment addresses) into the segment registers.

Table 3–11 Segment Register Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

lds{wl}

LDS

load far pointer using %ds

ldsl and ldsw invalid under -xarch=amd64

les{wl}

LES

load far pointer using %es

lesl and lesw invalid under -xarch=amd64

lfs{wl}

LFS

load far pointer using %fs

 

lgs{wl}

LGS

load far pointer using %gs

 

lss{wl}

LSS

load far pointer using %ss

 

Miscellaneous Instructions

The instructions documented in this section provide a number of useful functions.

Table 3–12 Miscellaneous Instructions

Solaris Mnemonic 

Intel/AMD Mnemonic 

Description 

Notes 

cpuid

CPUID

processor identification 

 

lea{wlq}

LEA

load effective address 

leaq valid only under -xarch=amd64

nop

NOP

no operation 

 

ud2

UD2

undefined instruction 

 

xlat

XLAT

table lookup translation 

 

xlatb

XLATB

table lookup translation