A P P E N D I X C - x86 Behavior and Implementation

A P P E N D I X C

x86 Behavior and Implementation

This appendix discusses x86/x64 and SPARC compatibility issues related to the floating-point units used in x86/x64 based systems.

x86/x64 based hardware include Pentium microprocessors and more recent microprocessors from Intel as well as compatible microprocessors from other manufacturers, such as the AMD Opteron processor. While great effort went into compatibility with the SPARC platform, several differences exist.

On x86/x64 based systems:

The x67 floating-point registers are 80 bits wide. Because intermediate results of arithmetic computations can be in double extended (80-bit) precision when the x87 floating-point register stack is in use, computation results can differ. The -fstore flag minimizes these discrepancies. However, using the -fstore flag introduces a penalty in performance.

Each time a single or double precision floating-point number is loaded onto the x87 floating-point register stack or stored into memory, a conversion to or from double extended (80-bit) precision occurs. Thus loads and stores of floating-point numbers can cause exceptions.

When the x87 floating-point register stack is in use, gradual underflow is implemented in hardware with microcode assist; there is no nonstandard mode.

The fpversion utility is not provided.

The double extended (80-bit) format admits certain bit patterns that do not represent any floating point values (see TABLE 2-8). The hardware generally treats these "unsupported formats" as signaling NaNs, but the math libraries are not consistent in their handling of such representations. Since these bit patterns are never generated by the hardware, they can only be created by invalid memory references (such as reading beyond the end of an array) or from explicit coercions of data in memory from one type to another (via C's union construct, for example). Therefore, in most numerical programs, these bit patterns do not arise.