Event Logs and POST Codes
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This chapter contains information about the BIOS event log, the BMC system event log, the power-on self test (POST), and console redirection. For more information on the BIOS event log and post codes, refer to the Sun Fire X4540 Server Service Manual (819-4359).
This chapter includes the following topics:
Viewing Event Logs
To view the BIOS event log and the BMC system event log.
1. Turn on main power so that all components are powered on . Use a non-conducting ball-point pen or stylus to press and release the Power button on the server front panel. See FIGURE 8-4.
When main power is applied to the full server, the Power/OK LED next to the Power button lights and remains lit.
2. Enter the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).
The BIOS Main menu screen is displayed.
3. View the BIOS event log:
a. From the BIOS Main Menu screen, select Advanced.
The Advanced Settings screen is displayed:
Main Advanced PCIPnP Boot Security Chipset Exit
********************************************************************************
* Advanced Settings * Options for CPU *
* *************************************************** * *
* WARNING: Setting wrong values in below sections * *
* may cause system to malfunction. * *
* * *
* * CPU Configuration * *
* * IDE Configuration * *
* * SuperIO Configuration * *
* * ACPI Configuration * *
* * Event Log Configuration * *
* * Hyper Transport Configuration * *
* * IPMI 2.0 Configuration * *
* * MPS Configuration * ** Select Screen *
* * PCI express Configuration * *
* * AMD PowerNow Configuration * ** Select Item *
* * Remote Access Configuration * Enter Go to Sub Screen *
* * USB Configuration * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* ******************************************************************************
Bios advanced screen main screen
b. From the Advanced Settings screen, select Event Log Configuration.
The Advanced Menu Event Logging Details screen is displayed.
Advanced
********************************************************************************
* Event Logging details * View all unread events *
* *************************************************** * on the Event Log. *
* View Event Log * *
* Mark all events as read * *
* Clear Event Log * *
* * *
* * *
* * *
* * *
* * *
* * *
* * *
* * ** Select Screen *
* * ** Select Item *
* * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
********************************************************************************
Bios Event Logging
c. From the Event Logging Details screen, select View Event Log.
All unread events are displayed.
4. View the BMC system event log:
a. From the BIOS Main Menu screen, select Advanced.
The Advanced Settings screen is displayed. See below.
b. From the Advanced Settings screen, select IPMI 2.0 Configuration.
The Advanced Menu IPMI 2.0 Configuration screen is displayed:
Advanced
********************************************************************************
* IPMI 2.0 Configuration * View all events in the *
* *************************************************** * BMC Event Log. *
* Status Of BMC Working * *
* * View BMC System Event Log * It will take up to *
* Reload BMC System Event Log * 60 Seconds approx. *
* Clear BMC System Event Log * to read all *
* * LAN Configuration * BMC SEL records. *
* * PEF Configuration * *
* BMC Watch Dog Timer Action [Disabled] * *
* * *
* * *
* * *
* * ** Select Screen *
* * ** Select Item *
* * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
********************************************************************************
IPMI configuration screen
c. From the IPMI 2.0 Configuration screen, select View BMC System Event Log.
The log takes about 60 seconds to generate, then it is displayed on the screen.
5. If the problem with the server is not evident, continue with Using the ILOM Service Processor GUI to View System Information, or Using IPMItool to View System Information.
About Power-On Self-Test (POST)
The system BIOS provides a rudimentary power-on self-test. After power on, POST does the following tasks:
- Checks the basic devices required for the server to operate
- Tests memory, tests the LSI SAS1068E disk controllers
- Probes and enumerates the attached disks
- Initializes the two Intel dual-gigabit Ethernet controllers
The progress of the self-test is indicated by a series of POST codes. These codes are displayed at the bottom right corner of the system’s VGA screen (after the self-test has progressed far enough to initialize the system video). However, the codes are displayed as the self-test runs and scroll off of the screen too quickly to be read (see POST Codes).
An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Redirecting Console Output).
This section includes the following topics:
BIOS POST Memory Test Overview
The BIOS POST memory test is performed as follows:
1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is shadowed (that is, copied from ROM to DRAM).
2. Once executing out of DRAM, the BIOS performs a simple memory test (a write/read of every location with the pattern 55aa55aa).
| Note - This memory test is performed only if Quick Boot is not enabled from the Boot Settings Configuration screen. Enabling Quick Boot causes the BIOS to skip the memory test. See Changing POST Options for more information.
|
| Note - Because the Sun Fire X4540 server can contain up to 64GB of memory, the memory test can take several minutes. You can escape from POST testing by pressing any key during POST.
|
3. The BIOS polls the memory controllers for both correctable and uncorrectable memory errors and logs those errors into the service processor.
Redirecting Console Output
Use the following instructions to access the service processor and redirect the console output so that the BIOS POST codes can be read.
1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).
The BIOS Main menu screen is displayed.
2. Select the Advanced menu tab.
The Advanced Settings screen is displayed.
3. Select IPMI 2.0 Configuration.
The IPMI 2.0 Configuration screen is displayed.
4. Select the LAN Configuration menu item.
The LAN Configuration screen is displayed.
5. Determine the server’s IP address:
a. Select the IP Assignment option that you want to use (DHCP or Static).
If you choose DHCP, the server’s IP address is retrieved from your network’s DHCP server and displayed using the following format:
Current IP address in BMC : xxx.xxx.xxx.xxx
If you choose Static to assign the IP address manually, perform the following steps:
b. Type the IP address in the IP Address field.
You can also enter the subnet mask and default gateway settings in their respective fields.
c. Select Commit and press Return to commit the changes.
d. Select Refresh and press Return to see your new settings displayed in the Current IP address in BMC field.
6. Start a web browser and type the service processor’s IP address in the browser’s URL field.
7. When you are prompted for a user name and password, type the following:
User Name: root
Password: changeme
The Sun Integrated Lights Out Manager main GUI screen is displayed.
8. Click the Remote Control tab.
9. Click the Redirection tab.
10. Set the color depth for the redirection console at either 6 or 8 bits.
11. Click the Start Redirection button.
12. When you are prompted for a user name and password, type the following:
User Name: root
Password: changeme
The current POST screen is displayed.
Changing POST Options
These instructions are optional, but you can use them to change the operations that the server performs during POST testing.
|
 To Change POST Options
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1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).
The BIOS Main menu screen is displayed.
2. Select Boot.
The Boot Settings screen is displayed.
Main Advanced PCIPnP Boot Security Chipset Exit
********************************************************************************
* Boot Settings * Configure Settings *
* *************************************************** * during System Boot. *
* * Boot Settings Configuration * *
* * *
* * Boot Device Priority * *
* * Hard Disk Drives * *
* * *
* * *
* * *
* * *
* * *
* * *
* * ** Select Screen *
* * ** Select Item *
* * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
********************************************************************************
Bios boot settings
3. Select Boot Settings Configuration.
The Boot Settings Configuration screen is displayed.
Boot
********************************************************************************
* Boot Settings Configuration * Allows BIOS to skip *
* *************************************************** * certain tests while *
* Quick Boot [Disabled] * booting. This will *
* System Configuration Display [Disabled] * decrease the time *
* Quiet Boot [Disabled] * needed to boot the *
* Language [English] * system. *
* AddOn ROM Display Mode [Force BIOS] * *
* Bootup Num-Lock [On] * *
* Wait For 'F1' If Error [Disabled] * *
* Interrupt 19 Capture [Disabled] * *
* * *
* * ** Select Screen *
* * ** Select Item *
* * +- Change Option *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
********************************************************************************
BIOS boot settings
4. On the Boot Settings Configuration screen, there are several options that you can enable or disable:
- Quick Boot - This option is disabled by default. If you enable this, the BIOS skips certain tests while booting, such as the extensive memory test. This decreases the time it takes for the system to boot.
- System Configuration Display - This option is disabled by default. If you enable this, the System Configuration screen is displayed before booting begins.
- Quiet Boot - This option is disabled by default. If you enable this, the Sun Microsystems logo is displayed instead of POST codes.
POST Codes
TABLE 13-1 contains descriptions of each of the POST codes, listed in the same order in which they are generated. These POST codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST codes listed in TABLE 13-1, the first two digits are from port 81 and the last two digits are from port 80.
TABLE 13-1 POST Codes
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Post Code
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Description
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00d0
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Coming out of POR, PCI configuration space initialization, Enabling 8111’s SMBus.
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00d1
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Keyboard controller BAT, Waking up from PM, Saving power-on CPUID in scratch CMOS.
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00d2
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Disable cache, full memory sizing, and verify that flat mode is enabled.
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00d3
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Memory detections and sizing in boot block, cache disabled, IO APIC enabled.
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01d4
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Test base 512KB memory. Adjust policies and cache first 8MB.
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01d5
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Bootblock code is copied from ROM to lower RAM. BIOS is now executing out of RAM.
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01d6
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Key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.
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01d7
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Restoring CPUID; moving bootblock-runtime interface module to RAM; determine whether to execute serial flash.
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01d8
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Uncompressing runtime module into RAM. Storing CPUID information in memory.
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01d9
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Copying main BIOS into memory.
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01da
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Giving control to BIOS POST.
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0004
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Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default values.
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00c2
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Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
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00c3
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Errata workarounds applied to the BSP (#78 & #110).
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00c6
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Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate.
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00c7
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HT sets link frequencies and widths to their final values.
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000a
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Initializing the 8042 compatible Keyboard Controller.
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000c
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Detecting the presence of Keyboard in KBC port.
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000e
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Testing and initialization of different Input Devices. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
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8600
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Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
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de00
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Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
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8613
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Initialize PM regs and PM PCI regs at Early-POST. Initialize multi host bridge, if system supports it. Setup ECC options before memory clearing. Enable PCI-X clock lines in the 8131.
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0024
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Uncompress and initialize any platform specific BIOS modules.
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862a
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BBS ROM initialization.
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002a
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Generic Device Initialization Manager (DIM) - Disable all devices.
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042a
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ISA PnP devices - Disable all devices.
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052a
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PCI devices - Disable all devices.
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122a
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ISA devices - Static device initialization.
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152a
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PCI devices - Static device initialization.
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252a
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PCI devices - Output device initialization.
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202c
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Initializing different devices. Detecting and initializing the video adapter installed in the system that has optional ROMs.
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002e
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Initializing all the output devices.
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0033
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Initializing the silent boot module. Set the window for displaying text information.
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0037
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Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
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4538
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PCI devices - IPL device initialization.
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5538
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PCI devices - General device initialization.
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8600
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Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
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POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. TABLE 13-2 describes the type of checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80.
TABLE 13-2 POST Code Checkpoints
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Post Code
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Description
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03
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Disable NMI, Parity, video for EGA, and DMA controllers. At this point, only ROM accesses are to the GPNV. If BB size is 64K, require to turn on ROM Decode below FFFF0000h. It should allow USB to run in E000 segment. The HT must program the NB specific initialization and OEM specific initialization can program if it need at beginning of BIOS POST, like overriding the default values of Kernel Variables.
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04
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Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259-compatible PICs in the system.
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05
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Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
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06
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Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
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C0
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Early CPU Init Start--Disable Cache--Init Local APIC.
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C1
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Set up boot strap processor information.
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C2
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Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
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C3
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Errata workarounds applied to the BSP (#78 & #110).
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C5
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Enumerate and set up application processors. This includes microcode loading and workarounds for errata (#78, #110, #106, #107, #69, #63).
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C6
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Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs are left in the CLI HLT state.
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C7
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The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming.
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0A
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Initializes the 8042 compatible Keyboard Controller.
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0B
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Detects the presence of PS/2 mouse.
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0C
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Detects the presence of Keyboard in KBC port.
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0E
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Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.
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13
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Initializes PM regs and PM PCI regs at Early-POST, Initializes multi host bridge, if system support it. Setup ECC options before memory clearing. REDIRECTION causes corrected data to written to RAM immediately. CHIPKILL provides 4 bit error det/corr of x4 type memory. Enable PCI-X clock lines in the 8131.
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20
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Relocate all the CPUs to a unique SMBASE address. The BSP will be set to have its entry point at A000:0. If less than 5 CPU sockets are present on a board, subsequent CPUs entry points will be separated by 8000h bytes. If more than 4 CPU sockets are present, entry points are separated by 200h bytes. CPU module will be responsible for the relocation of the CPU to correct address. NOTE: APs are left in the INIT state.
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24
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Uncompress and initialize any platform-specific BIOS modules.
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30
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Initializes System Management Interrupt.
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2A
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Initializes different devices through DIM.
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2C
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Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
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2E
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Initializes all the output devices.
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31
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Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initializes language and font modules for ADM. Activate ADM module.
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33
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Initializes the silent boot module. Sets the window for displaying text information.
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37
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Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
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38
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Initializes different devices through DIM.
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39
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Initializes DMAC-1 and DMAC-2.
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3A
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Initialize RTC date/time.
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3B
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Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
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3C
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By this point, RAM read/write test is completed, program memory holes or handle any adjustments needed in RAM size with respect to NB. Test if HT Module found an error in BootBlock and CPU compatibility for MP environment.
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40
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Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, ... etc.) successfully installed in the system and update the BDA, EBDA, ... etc.
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50
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Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
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52
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Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.
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60
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Initializes NUM-LOCK status and programs the KBD typematic rate.
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75
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Initializes Int-13 and prepare for IPL detection.
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78
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Initializes IPL devices controlled by BIOS and option ROMs.
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7A
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Initializes remaining option ROMs.
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7C
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Generate and write contents of ESCD in NVRam.
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84
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Log errors encountered during POST.
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85
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Display errors to the user and gets the user response for error.
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87
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Execute BIOS setup if needed/requested.
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8C
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After all device initialization is done, programmed any user selectable parameters relating to NB/SB, such as timing parameters, non-cacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node.
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8D
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Build ACPI tables (if ACPI is supported).
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8E
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Program the peripheral parameters. Enable/Disable NMI as selected.
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90
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Late POST initialization of system management interrupt.
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A0
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Check boot password if installed.
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A1
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Clean-up work needed before booting to OS.
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A2
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Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.
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A4
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Initialize runtime language module.
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A7
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Displays the system configuration screen if enabled. Initialize the CPUs before boot, which includes the programming of the MTRRs.
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A8
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Prepare CPU for OS boot including final MTRR values.
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A9
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Wait for user input at config display if needed.
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AA
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Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
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AB
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Prepare BBS for Int 19 boot.
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AC
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Any kind of Chipsets (NB/SB) specific programming needed during End- POST, just before giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming needed during End-POST. Copy OEM specific data from POST_DSEG to RUN_CSEG.
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B1
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Save system context for ACPI.
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00
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Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLIHLT state.
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61-70
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OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may be different from one platform to the next.
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| Sun Fire X4500/X4540 Servers Diagnostics Guide
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819-4363-12
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Copyright © 2009 Sun Microsystems, Inc. All rights reserved.