When the type suffix is not included in a multiply or divide instruction, it defaults to a long.

imulb r/m8 imulw r/m16 imul{l} r/m32 imul{wl} r/m[16|32], reg[16|32] imul{bwl} imm[16|32], r/m[16|32], reg[16|32]

r/m8 x AL -> AX r/m16 x AX -> DX:AX

r/m32 x EAX -> EDX:EAX r/m[16|32] x reg[16|32] -> reg|16|32]

imm[16|32] x r/m[16|32] -> reg|16|32]

The single-operand form of `imul` executes a signed multiply of a byte, word, or long by the contents of the AL, AX, or EAX register and stores the product in the AX, DX:AX or EDX:EAX register respectively.

The two-operand form of `imul` executes a signed multiply of a register or memory word or long by a register word or long and stores the product in that register word or long.

The three-operand form of `imul` executes a signed multiply of a 16- or 32-bit immediate by a register or memory word or long and stores the product in a specified register word or long.

`imul` clears the overflow and carry flags under the following conditions:

Instruction Form |
Condition for Clearing OF and CF |
---|---|

r/m8 x AL -> AX |
AL = sign-extend of AL to 16 bits |

r/m16 x AX -> DX:AX |
AX= sign-extend of AX to 32 bits |

r/m32 x EAX -> EDX:EAX |
EDX:EAX= sign-extend of EAX to 32 bits |

r/m[16|32] x reg[16|32] -> reg|16|32] |
Product fits exactly within reg[16|32] |

imm[16|32] x r/m[16|32] -> reg|16|32] |
Product fits exactly within reg[16|32] |

Perform an 8-bit signed multiply of the AL register and the contents of the effective address (addressed by the ESI register plus an offset of 1):

imulb 1(%esi)

Perform a 16-bit signed multiply of the constant, -126, and the contents of the effective address (addressed by the EDI register plus an offset of 4). Store the result in the DX register:

imulw $-126, 4(%edi), %dx

Perform a 32-bit signed multiply of the constant, 12345678, and the contents of the effective address (addressed by the EDI register plus an offset of 4). Store the result in the EDX register:

imull $12345678, 4(%edi), %edx

mul{bwl} r/m[8|16|32]

r/m8 x AL -> AX

r/m16 x AX -> DX:AX

r/m32 x EAX -> EDX:EAX

`mul` executes a unsigned multiply of a byte, word, or long by the contents of the AL, AX, or EAX register and stores the product in the AX, DX:AX or EDX:EAX register respectively.

`mul` clears the overflow and carry flags under the following conditions:

Instruction Form |
Condition for Clearing OF and CF |
---|---|

r/m8 x AL -> AX |
clear to 0 if AH is 0; otherwise, set to 1 |

r/m16 x AX -> DX:AX |
clear to 0 if DX is 0; otherwise, set to 1 |

r/m32 x EAX -> EDX:EAX |
clear to 0 if EDX is 0; otherwise, set to 1 |

Perform an 8-bit unsigned multiply of the AL register and the contents of the effective address (addressed by the ESI register plus an offset of 1):

mulb 1(%esi)

Perform a 16-bit unsigned multiply of the AL register and the contents of the effective address (addressed by the EDI register plus an offset of 4):

mulw 4(%edi)

Perform a 32-bit unsigned multiply of the AL register and the contents of the effective address (addressed by the EDI register plus an offset of 1):

mull 1(%edi)

div{bwl} r/m[8|16|32]

AX r/m8 -> AL DX:AX

r/m16 -> AX EDX:EAX

r/m32 -> EAX

`div` executes unsigned division. `div` divides a 16-, 32-, or 64-bit register value (dividend) by a register or memory byte, word, or long (divisor). The quotient is stored in the AL, AX, or EAX register respectively.

The remainder is stored in AH, Dx, or EDX. The size of the divisor (8-, 16- or 32-bit operand) determines the particular register used as the dividend.

The OF, SF, ZF, AR, PF and CF flags are undefined.

Perform an 8-bit unsigned divide of the AX register by the contents of the effective address (addressed by the ESI register plus an offset of 1) and store the quotient in the AL register, and the remainder in AH:

divb 1(%esi)

Perform a 16-bit unsigned divide of the DX:AX register by the contents of the effective address (addressed by the EDI register plus an offset of 4) and store the quotient in the AX register, and the remainder in DX:

divw 4(%edi)

Perform a 32-bit unsigned divide of the EDX:EAX register by the contents of the effective address (addressed by the EDI register plus an offset of 4) and store the quotient in the EAX register, and the remainder in EDX:

divl 4(%edi)

idiv{bwl} r/m[8|16|32]

AX r/m8 -> AL

DX:AX r/m16 -> AX

EDX:EAX r/m32 -> EAX

`idiv` executes signed division. `idiv` divides a 16-, 32-, or 64-bit register value (dividend) by a register or memory byte, word, or long (divisor). The size of the divisor (8-, 16- or 32-bit operand) determines the particular register used as the dividend, quotient,
and remainder.

Divisor Operand Size |
Dividend |
Quotient |
Remainder |
---|---|---|---|

byte |
AX |
AL |
AH |

word |
DX:AX |
AX |
DX |

long |
EDX:EAX |
EAX |
EDX |

If the resulting quotient is too large to fit in the destination, or if the divisor is 0, an Interrupt 0 is generated. Non-integral quotients are truncated toward 0. The remainder has the same sign as the dividend; the absolute value of the remainder is always less than the absolute value of the divisor.

Perform a 16-bit signed divide of the DX:AX register by the contents of the effective address (addressed by the EDI register plus an offset of 4) and store the quotient in the AX register

divw 4(%edi)

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