r/m16 (masked by FF00) -> r16
r/m32 (masked by 00FxFF00) -> r32
If the selector is visible at the CPL (modified by the RPL) and is a valid descriptor type, lar stores a form of the second doubleword of the descriptor for the source selector. The designated register is loaded with the double-word (high-order) of the descriptor masked by 00FxFF00, and the zero flag is set to 1. The x in 00Fx ... indicates that these four bits loaded by lar are undefined. The zero flag is cleared if the selector is invisible or of the wrong type.
The 32-bit value is stored in the 32-bit destination register if the 32-bit operand size is specified. If the 16-bit operand size is specified, the lower 16-bits of this value are stored in the 16-bit destination register.
For lar, all data segment descriptors and code are valid.
Load access rights from the contents of the effective address (addressed by the EBX register plus an offset of 5) into the EDX register:
lar 5(%ebx), %edx