Overview of Network Traffic Flow

Packets traverse a path when they flow into or out of a system. On a granular level, packets are received and transmitted through receive (Rx) rings and transmit (Tx) rings of a NIC. From these rings, received packets are passed up the network stack for further processing while outbound packets are sent to the network.

Chapter 19, Managing Network Resources introduces the concept of network lanes. A combination of system resources that are allocated to manage network traffic constitutes a network lane. Thus, network lanes are customized paths for specific types of network traffic. Each lane can be either a hardware lane or a software lane. In addition, each lane type can be either a receive lane or a transmit lane. The distinction between hardware and software lanes is based on a NIC's ability to support ring allocation. For more information about ring allocation, see Transmit and Receive Rings. This chapter focuses primarily on incoming traffic that is received through receive lanes.

On hardware lanes, rings are dedicated to the packets that use those lanes. In contrast, rings on software lanes are shared among datalinks. Datalinks are configured to share rings for the following reasons:

• Administrative intent. The datalink might not be performing intensive processes to require dedicated rings.

• The NIC does not support ring allocation.

• Despite support for ring allocation, rings are no longer available to be assigned for exclusive use.

Consider the following figure that shows different hardware lanes:

Figure 20-1 Hardware Lanes

The figure shows the following configuration:

• The system has a single NIC, nxge.

• Links are configured over the physical device: nxge0, vnic1, and vnic2. Note that as a datalink, nxge0 can be assigned a customized name. However, in the figure, the link retains its default device name.

• The system has multiple CPUs.

• The NIC supports dynamic ring allocation. Thus, a set of hardware rings can be assigned to each link to constitute a hardware lane. In addition, a set of CPUs is also allocated to each lane.