E.2 SPARC-V9 Instruction Set Changes
Application software written for the SPARC-V8 processor runs unchanged on a SPARC-V9 processor.
E.2.1 Extended Instruction Definitions to Support the 64-Bit Model
Table E-5 Extended Instruction Definitions
FCMP,
FCMPE |
Floating-Point Compare – can set any of the four floating-point condition codes. |
LDFSR, STFSR |
Load/Store
FSR- only affect low-order 32 bits of FSR |
LDUW, LDUWA |
Same as LD, LDA
in SPARC-V8 |
RDASR/WRASR |
Read/Write State Registers - access additional registers |
SAVE/RESTORE |
|
SETHI |
|
SRA, SRL, SLL, Shifts |
Split into
32-bit and 64-bit versions |
Tcc |
(was Ticc) Operates with either the 32-bit integer condition
codes (icc), or the 64-bit integer condition codes (xcc) |
|
All other arithmetic operations operate on 64-bit operands and produce 64-bit results.
E.2.2 Added Instructions to Support 64 Bits
Table E-6 Added 64–Bit Instructions
F[sdq]TOx |
Convert floating
point to 64-bit word |
FxTO[sdq] |
Convert 64-bit word to floating point |
FMOV[dq] |
Floating-Point Move, double and
quad |
FNEG[dq] |
Floating-point Negate, double and quad |
FABS[dq] |
Floating-point Absolute Value, double and quad |
LDDFA, STDFA, LDFA,
STFA |
Alternate address space forms of LDDF, STDF, LDF, and STF |
LDSW |
Load a signed
word |
LDSWA |
Load a signed word from an alternate space |
LDX |
Load an extended word |
LDXA |
Load an
extended word from an alternate space |
LDXFSR |
Load all 64 bits of the FSR
register |
STX |
Store an extended word |
STXA |
Store an extended word into an alternate space |
STXFSR |
Store all
64 bits if the FSR register |
|
E.2.3 Added Instructions to Support High-Performance System Implementation
Table E-7 Added High-Performance System Instructions
BPcc |
Branch on integer condition code with prediction |
BPr |
Branch
on integer register contents with prediction |
CASA, CASXA |
Compare and Swap from an alternate
space |
FBPfcc |
Branch on floating-point condition code with prediction |
FLUSHW |
Flush windows |
FMOVcc |
Move floating-point register if condition
code is satisfied |
FMOVr |
Move floating-point register if integer register satisfies condition |
LDQF(A), STQF(A) |
Load/Store Quad
Floating-point (in an alternate space) |
MOVcc |
Move integer register if condition code is satisfied |
MOVr |
Move
integer register if register contents satisfy condition |
MULX |
Generic 64-bit multiply |
POPC |
Population count |
PREFETCH, PREFETCHA |
Prefetch Data |
SDIVX,
UDIVX |
Signed and Unsigned 64-bit divide |
|
E.2.4 Deleted Instructions
Table E-8 Deleted Instructions
Coprocessor loads and stores |
|
RDTBR and WRTBR |
TBR no longer
exists. It is replaced by TBA, which can be read/written with RDPR/WRPR instructions |
RDWIM
and WRWIM |
WIM no longer exists. WIM has been replaced by several register-window registers |
REPSR
and WRPSR |
PSR no longer exists. It has been replaced by several separate
registers that are read/written with other instructions |
RETT |
Return from trap (replace by DONE/RETRY) |
STDFQ |
Store Double
from Floating-point Queue (replaced by the RDPR FQ instruction |
|
E.2.5 Miscellaneous Instruction Changes
Table E-9 Changed Instructions
IMPDEPn |
(Changed) Implementation-dependent instructions (replace
SPARC-V8 CPop instructions) |
MEMBAR |
(Added) Memory barrier (memory synchronization support) |
|