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Sun Blade X3-2B (formerly Sun Blade X6270 M3) Service Manual
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Document Information

Using This Documentation

Sun Blade X3-2B Model Name Change

Getting the Latest Firmware and Software

Documentation and Feedback

About This Documentation

Support and Training

Contributors

Change History

Service Manual Overview

About the Sun Blade X3-2B

Product Description

Front Panel Features

Front Panel LEDs and Buttons

Rear Panel Features

About the System Chassis

About Oracle ILOM

About the Chassis Monitoring Module (CMM)

Replaceable Server Module Components

Preparing the Sun Blade X3-2B for Service

Obtaining the Server Module Serial Number

Powering Off the Server Module

Performing ESD and Antistatic Prevention Measures

Set Up for ESD Prevention

Managing the Locate LED

Remove the Server Module from the Sun Blade Chassis

Remove the Server Module Top Cover

Removing or Inserting Filler Panels

About the Multi-port Cable

Attach a Dongle Cable

Servicing Sun Blade X3-2B Components

Servicing a Storage Drive (CRU)

Servicing DIMMs (CRU)

Replace the System Battery (CRU)

Servicing USB Flash Drives (CRU)

Servicing a Fabric Expansion Module (CRU)

Servicing a RAID Expansion Module (CRU)

Servicing Cables (CRU)

Servicing a Processor and Heat Sink Assembly (FRU)

Servicing the Motherboard Assembly (FRU)

Returning Sun Blade X3-2B to Operation

Install the Server Module Top Cover

Install the Sun Blade X3-2B in the Chassis

Powering On the Server Module

Troubleshooting the Sun Blade X3-2B

Diagnosing Server Module Hardware Faults

Troubleshooting Using LED Status Indicators

Using the DIMM and Processor Test Circuit

Troubleshooting Server Module Power States

Firmware and Software Troubleshooting

BIOS Power-On Self-Test (POST) Checkpoints

About POST Code Checkpoint Memory Testing

Viewing POST Code Checkpoints

View BIOS POST Code Checkpoints Using Oracle ILOM Web Interface

View BIOS POST Code Checkpoints Using Oracle ILOM CLI

POST Code Checkpoint Reference

Getting Server Firmware and Software

Firmware and Software Updates

Firmware and Software Access Options

Available Software Release Packages

Accessing Firmware and Software

Installing Updates

Index

POST Code Checkpoint Reference

POST (power-on self-test) works with other processes to complete initialization of the host system prior to booting. During the host initialization process, if failures occur, the failures are communicated to the service processor (SP) for analysis and logging.

The following table describes each POST code, listed in the order in which they are generated. POST codes appear at the bottom right of the BIOS screen as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST checkpoint codes listed in this section, the first two digits are from port 81 and the last two digits are from port 80.

The Response column describes the action taken by the system on encountering the corresponding error. The actions are:

Checkpoint Ranges
Status Code Range
Description
0x01 — 0x0B
SEC execution
0x0C – 0x0F
SEC errors
0x10 — 0x2F
PEI execution up to and including memory detection
0x30 - 0x4F
PEI execution after memory detection
0x50 - 0x5F
PEI errors
0x60 - 0x8F
DXE execution up to BDS
0x90 - 0xCF
BDS execution
0xD0 - 0xDF
DXE errors
0xE0 - 0xE8
S3 Resume (PEI)
0xE9 - 0xEF
S3 Resume errors (PEI)
0xF0 - 0xF8
Recovery (PEI)
0xF9 - 0xFF
Recovery errors (PEI)
Standard Checkpoints: SEC Phase
SEC Phase
Status Code
Description
0x00
Not used
Progress Codes
0x00
Power on. Reset type detection (soft/hard).
0x02
AP initialization before microcode loading
0x03
North Bridge initialization before microcode loading
0x04
South Bridge initialization before microcode loading
0x05
OEM initialization before microcode loading
0x06
Microcode loading
0x07
AP initialization after microcode loading
0x08
North Bridge initialization after microcode loading
0x09
South Bridge initialization after microcode loading
0x0A
OEM initialization after microcode loading
0x0B
Cache initialization
SEC Error Codes
0x0C — 0x0D
Reserved for future AMI SEC error codes
0x0E
Microcode not found
0x0F
Microcode not loaded
SEC Beep Codes
None
Standard Checkpoints: PEI Phase
PEI Phase
Status Code
Description
Progress Codes
0x10
PEI Core is started
0x11
Pre-memory CPU initialization is started
0x12
Pre-memory CPU initialization (CPU module specific)
0x13
Pre-memory CPU initialization (CPU module specific)
0x14
Pre-memory CPU initialization (CPU module specific)
0x15
Pre-memory North Bridge initialization is started
0x16
Pre-Memory North Bridge initialization (North Bridge module specific)
0x17
Pre-Memory North Bridge initialization (North Bridge module specific)
0x18
Pre-Memory North Bridge initialization (North Bridge module specific)
0x19
Pre-memory South Bridge initialization is started
0x1A
Pre-memory South Bridge initialization (South Bridge module specific)
0x1B
Pre-memory South Bridge initialization (South Bridge module specific)
0x1C
Pre-memory South Bridge initialization (South Bridge module specific)
0x1D - 0x2A
OEM pre-memory initialization codes
0x2B
Memory initialization. Serial Presence Detect (SPD) data reading
0x2C
Memory initialization. Memory presence detection
0x2D
Memory initialization. Programming memory timing information
0x2E
Memory initialization. Configuring memory
0x2F
Memory initialization (other).
0x30
Reserved for ASL (see ASL Status Codes section below)
0x31
Memory Installed
0x32
CPU post-memory initialization is started
0x33
CPU post-memory initialization. Cache initialization
0x34
CPU post-memory initialization. Application Processor(s) (AP) initialization
0x35
CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36
CPU post-memory initialization. System Management Mode (SMM) initialization
0x37
Post-Memory North Bridge initialization is started
0x38
Post-Memory North Bridge initialization (North Bridge module specific)
0x39
Post-Memory North Bridge initialization (North Bridge module specific)
0x3A
Post-Memory North Bridge initialization (North Bridge module specific)
0x3B
Post-Memory South Bridge initialization is started
0x3C
Post-Memory South Bridge initialization (South Bridge module specific)
0x3D
Post-Memory South Bridge initialization (South Bridge module specific)
0x3E
Post-Memory South Bridge initialization (South Bridge module specific)
0x3F-0x4E
OEM post memory initialization codes
0x4F
DXE IPL is started
PEI Error Codes
0x50
Memory initialization error. Invalid memory type or incompatible memory speed
0x51
Memory initialization error. SPD reading has failed
0x52
Memory initialization error. Invalid memory size or memory modules do not match.
0x53
Memory initialization error. No usable memory detected
0x54
Unspecified memory initialization error.
0x55
Memory not installed
0x56
Invalid CPU type or speed.
0x57
CPU mismatch
0x58
CPU self test failed or possible CPU cache error
0x59
CPU micro-code is not found or micro-code update is failed
0x5A
Internal CPU error
0x5B
reset PPI is not available
0x5C-0x5F
Reserved for future AMI error codes
S3 Resume Progress Codes
0xE0
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
0xE1
S3 Boot Script execution
0xE2
Video repost
0xE3
OS S3 wake vector call
0xE4-0xE7
Reserved for future AMI progress codes
S3 Resume Error Codes
0xE8
S3 Resume Failed
0xE9
S3 Resume PPI not Found
0xEA
S3 Resume Boot Script Error
0xEB
S3 OS Wake Error
0xEC-0xEF
Reserved for future AMI error codes
Recovery Progress Codes
0xF0
Recovery condition triggered by firmware (Auto recovery)
0xF1
Recovery condition triggered by user (Forced recovery)
0xF2
Recovery process started
0xF3
Recovery firmware image is found
0xF4
Recovery firmware image is loaded
0xF5 – 0xF7
Reserved for future AMI progress codes
Recovery Error Codes
0xF8
Recovery PPI is not available
0xF9
Recovery capsule is not found
0xFA
Invalid recovery capsule
0xFB — 0xFF
Reserved for future AMI error codes
PEI Beep Codes
# of Beeps
Description
1
Memory not Installed
1
Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)
2
Recovery started
3
DXEIPL was not found
3
DXE Core Firmware Volume was not found
4
Recovery failed
4
S3 Resume failed
7
Reset PPI is not available
Standard Checkpoints: DXE Phase
DXE Phase
Status Code
Description
0x60
DXE Core is started
0x61
NVRAM initialization
0x62
Installation of the South Bridge Runtime Services
0x63
CPU DXE initialization is started
0x64
CPU DXE initialization (CPU module specific)
0x65
CPU DXE initialization (CPU module specific)
0x66
CPU DXE initialization (CPU module specific)
0x67
CPU DXE initialization (CPU module specific)
0x68
PCI host bridge initialization
0x69
North Bridge DXE initialization is started
0x6A
North Bridge DXE SMM initialization is started
0x6B
North Bridge DXE initialization (North Bridge module specific)
0x6C
North Bridge DXE initialization (North Bridge module specific)
0x6D
North Bridge DXE initialization (North Bridge module specific)
0x6E
North Bridge DXE initialization (North Bridge module specific)
0x6F
North Bridge DXE initialization (North Bridge module specific)
0x70
South Bridge DXE initialization is started
0x71
South Bridge DXE SMM initialization is started
0x72
South Bridge devices initialization
0x73
South Bridge DXE Initialization (South Bridge module specific)
0x74
South Bridge DXE Initialization (South Bridge module specific)
0x75
South Bridge DXE Initialization (South Bridge module specific)
0x76
South Bridge DXE Initialization (South Bridge module specific)
0x77
South Bridge DXE Initialization (South Bridge module specific)
0x78
ACPI module initialization
0x79
CSM initialization
0x7A - 0x7F
Reserved for future AMI DXE codes
0x80 - 0x8F
OEM DXE initialization codes
0x90
Boot Device Selection (BDS) phase is started
0x91
Driver connecting is started
0x92
PCI Bus initialization is started
0x93
PCI Bus Hot Plug Controller Initialization
0x94
PCI Bus Enumeration
0x95
PCI Bus Request Resources
0x96
PCI Bus Assign Resources
0x97
Console Output devices connect
0x98
Console input devices connect
0x99
Super IO Initialization
0x9A
USB initialization is started
0x9B
USB Reset
0x9C
USB Detect
0x9D
USB Enable
0x9E - 0x9F
Reserved for future AMI codes
0xA0
IDE initialization is started
0xA1
IDE Reset
0xA2
IDE Detect
0xA3
IDE Enable
0xA4
SCSI initialization is started
0xA5
SCSI Reset
0xA6
SCSI Detect
0xA7
SCSI Enable
0xA8
Setup Verifying Password
0xA9
Start of Setup
0xAA
Reserved for ASL (see ASL Status Codes section below)
0xAB
Setup Input Wait
0xAC
Reserved for ASL (see ASL Status Codes section below)
0xAD
Ready To Boot event
0xAE
Legacy Boot event
0xAF
Exit Boot Services event
0xB0
Runtime Set Virtual Address MAP Begin
0xB1
Runtime Set Virtual Address MAP End
0xB2
Legacy Option ROM Initialization
0xB3
System Reset
0xB4
USB hot plug
0xB5
PCI bus hot plug
0xB6
Clean-up of NVRAM
0xB7
Configuration Reset (reset of NVRAM settings)
0xB8 - 0xBF
Reserved for future AMI codes
0xC0 - 0xCF
OEM BDS initialization codes
DXE Error Codes
0xD0
CPU initialization error
0xD1
North Bridge initialization error
0xD2
South Bridge initialization error
0xD3
Some of the Architectural Protocols are not available
0xD4
PCI resource allocation error. Out of Resources
0xD5
No Space for Legacy Option ROM
0xD6
No Console Output Devices are found
0xD7
No Console Input Devices are found
0xD8
Invalid password
0xD9
Error loading Boot Option (LoadImage returned error)
0xDA
Boot Option is failed (StartImage returned error)
0xDB
Flash update is failed
0xDC
Reset protocol is not available
DXE Beep Codes
# of Beeps
Description
1
Invalid password
4
Some of the Architectural Protocols are not available
5
No Console Output Devices are found
5
No Console Input Devices are found
6
Flash update is failed
7
Reset protocol is not available
8
Platform PCI resource requirements cannot be met
ACPI/ASL Checkpoints
ACPI/ASL Checkpoints
Status Code
Description
0x01
System is entering S1 sleep state
0x02
System is entering S2 sleep state
0x03
System is entering S3 sleep state
0x04
System is entering S4 sleep state
0x05
System is entering S5 sleep state
0x10
System is waking up from the S1 sleep state
0x20
System is waking up from the S2 sleep state
0x30
System is waking up from the S3 sleep state
0x40
System is waking up from the S4 sleep state
0xAC
System has transitioned into ACPI mode. Interrupt controller is in PIC mode.
0xAA
System has transitioned into ACPI mode. Interrupt controller is in APIC mode.
OEM-Reserved Checkpoint Ranges
OEM-Reserved Checkpoint Ranges
Status Code
Description
0x05
OEM SEC initialization before microcode loading
0x0A
OEM SEC initialization after microcode loading
0x1D - 0x2A
OEM pre-memory initialization codes
0x3F - 0x4E
OEM PEI post memory initialization codes
0x80 - 0x8F
OEM DXE initialization codes
0xC0 - 0xCF
OEM BDS initialization codes