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Oracle® Communications Network Integrity Optical Circuit Assimilation Cartridge Guide
Release 7.1

E23715-01
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6 Design Studio Construction

This chapter provides information on the composition of the Oracle Communications Network Integrity Optical Circuit Assimilation cartridge from the Oracle Communications Design Studio perspective.

Model Collection

The Optical Circuit Assimilation cartridge uses the Optical Model for its model collection. See Network Integrity Developer's Guide for more information.

Actions

The following tables outline the Design Studio construction of the Optical Circuit Assimilation cartridge actions and associated components.

Table 6-1 shows the Design Studio construction of the actions for the Optical Circuit Assimilation cartridge.

Table 6-1 Actions Design Studio Construction

Action Name Result Category Address Handler UI Parameters Processors

Assimilate Optical Circuits (assimilation)

Device

N/A

See Table 6-2

See Table 6-3

Discrepancy Detection

OpticalAssimilation

N/A

None

See Table 6-4


Table 6-2 shows the Design Studio construction of the UI parameters belonging to the Optical Circuit Assimilation cartridge.

Table 6-2 Cartridge UI Parameters Design Studio Construction

Parameter Name Type Description UI Label

assimilateVC12

Drop down

Select True to run the VC12 LOT LOP Assimilator processor. Values are True or False.

Assimilate VC12

assimilateVC3

Drop down

Select True to run the VC3 LOT LOP Assimilator processor. Values are True or False.

Assimilate VC3

processDiscoveryResults

Drop down

Causes the Optical Assimilation Initializer processor to convert the input results to the Intermediate Assimilation Model. If you are running a hierarchical set of assimilation scans, set this field to True for the first assimilation scan. Values are True or False.

Process Discovery Results

modelIncompleteCircuits

Drop down

Causes the Optical Assimilation Modeler processor to convert complete and partial circuits from the Intermediate Assimilation Model. If you are running a hierarchical set of assimilation scans, set this field to True on the last assimilation scan. Values are True or False.

Model Incomplete Circuits

isTopLevelAssimilation

Drop down

Indicates whether the assimilation scan is being run on the top and final level of the hierarchy. When this field is set to False, the circuit matcher matches circuit names for complete circuits only. When this field is set to True, the circuit matcher also matches partial circuits. Values are True or False.

Is Top Level Assimilation


Table 6-3 shows the Design Studio construction of the processors belonging to the Assimilate Optical Circuits action.

Table 6-3 Optical Circuit Assimilation Processors Design Studio Construction

Processor Name Variable

Layer Rate Initializer

Input: N/A

Output: layerRates

Optical Assimilation Initializer

Input: layerRates

Output: N/A

Optical VC4 HOT HOP Assimilator

Input: N/A

Output:

  • assimilateVC3

    Configured UI parameter specifying whether to assimilate VC3s.

  • assimilateVC12

    Configured UI parameter specifying whether to assimilate VC12s.

  • scansInScope

    The list of scanRunIds in the assimilation scope, excluding the discovery scan run ID (toplevel).

Optical VC3 LOT LOP Assimilator

Input: scansInScope

Output: N/A

Optical VC12 LOT LOP Assimilator

Input: scansInScope

Output: N/A

Page Initialization For Circuit

Input: scansInScope

Output:

  • devicePipeMap

    A mapping of managed element (ME) names to circuit pipes.

  • linkPages

    The total number of links page based on page size.

  • pageSize

    The size of each page.

  • pages

    The total number of Circuit pages based on page size.

Optical Assimilation Circuit Matcher

Input: N/A

Output: N/A

Optical Assimilation Modeler

Input: N/A

Output: N/A

Optical Assimilation Persister

Input: devicePipeMap, pageIndex, pageSize, scansInScope

Output: N/A

Link Modeler

Input: devicePipeMap

Output: N/A

Link Persister

Input: devicePipeMap, linkPageIndex, pageSize, scansInScope

Output: N/A

Cleanup Processor

Input: N/A

Output: N/A


Table 6-4 shows the Design Studio construction of the processors belonging to the Discrepancy Detection action.

Table 6-4 Discrepancy Detection Processors Design Studio Construction

Processor Name Variable

Circuit Discrepancy Name Filter Initializer

Input: N/A

Output:

  • isTopLevel

    Configured UI parameter specifying whether the scan configuration is the top level scan.

Missing Entity Filter Initializer

Input: isTopLevel

Output: N/A

DiscrepancyDetector

Input: N/A

Output: N/A