fbe - assembler
fbe [ -hwcap={1|0} ] [ -L ] [ -m ] [ -m32 ] [ -m64 ]
[ -n ] [ -o outfile ] [ -ul ] [ -P ]
[ -Dname ] [ -Dname=def ] [ -Ipath ]
[ -Uname.... ] [ -Q[y|n] ] [ -s ]
[ -S[a|b|c|l|A|B|C|L]] [ -V ] [ -xarch=v ]
[ -xdecouple=[dcti,no%dcti] ] [ -xF ] [ -Y[m|c],path ]
[ -YI,path ] filename...
fbe [ -a32 ] [ -m ] [ -m32 ] [ -m64 ] [ -n ]
[ -H ] [ -nH ] [ -o outfile ]
[ -P ] [ -Dname ] [ -Dname=def ] [ -Ipath ] [ -Uname...]
[ -KPIC ] [ -Q[y|n] ] [ -remove_empty_sect ]
[ -s ] [ -S[a|b|c|l|A|B|C|L]] [ -V ]
[ -xchip=v ] [ -xmodel=[a] ]
[ -Y[m|d],path ] [ -YI,path ] filename...
SPROlang
The fbe command creates object files from assembly language source files.
The following flags are common to both SPARC and x86. They may be specified in any order.
When the -P option is in effect, these options are passed to the cpp (1) preprocessor without interpretation by the fbe command; otherwise, they are ignored.
When the -P option is in effect, this option is passed to the cpp (1) preprocessor without interpretation by the fbe command; otherwise, it is ignored.
Instructs fbe to ignore line-number information from the preprocessor.
Run the m4 (1) macro processor on the input to the assembler.
Generate 32-bit or 64-bit ELF format object code.
Suppress all the warnings while assembling.
Put the output of the assembly in outfile. By default, the output file name is formed by removing the .s suffix, if there is one, from the input file name and appending a .o suffix.
Run cpp (1) , the C preprocessor, on the files being assembled. The preprocessor is run separately on each input file, not on their concatenation. The preprocessor output is passed to the assembler.
If the y option is specified, it produces the "assembler version" information in the comment section of the output object file. If the n option is specified, the information is suppressed.
Produces a disassembly of the emitted code to the standard output. Adding each of the following characters to the -S option produces:
disassembling with address
disassembling with .bof
disassembling with comments
disassembling with line numbers
Capital letters switch the corresponding option off. The default is -Sc.
Place all stabs in the .stabs section. By default, stabs are placed in stabs.excl sections, which are stripped out by the static linker, ld (1) , during final execution. When the -s option is used, stabs remain in the final executable because .stab sections are not stripped by the static linker.
When the -P option is in effect, this option is passed to the cpp (1) preprocessor without interpretation by the fbe command; otherwise, it is ignored.
Specify path to the version of m4 to use.
Indicate path to search for #include header files.
Enable (1) or suppress (0) the generation of the Hardware Capabilities section. Default is to generate the section.
Save all symbols, including temporary labels that are normally discarded to save space, in the ELF symbol table.
Treat all undefined symbols as local.
Specify path to the version of cpp to use.
Enables the assembler to accept instructions defined in the SPARC-V9 architecture. The resulting object code is in ELF32 format when compiled with -m32, ELF64 format with -m64. It will not execute on a Oracle Solaris V8 system (a machine with a V8 processor). It will execute on a Oracle Solaris V8+ system.
Enables the assembler to accept instructions defined in the SPARC-V9 architecture plus the instructions in the Visual Instruction Set (VIS) version 1.0. The resulting object code is in V8+ ELF32 format when compiled with -m32, ELF64 format with -m64. It will not execute on a Oracle Solaris system with a V8 processor. It will execute on a Oracle Solaris system with a V8+ processor.
Enables the assembler to accept instructions defined in the SPARC-V9 architecture, plus the instructions in the Visual Instruction Set (VIS) version 2.0, with UltraSPARC-III extensions. The resulting object code is in V8+ ELF32 format when compiled with -m32, ELF64 format with -m64.
Accept instructions defined for the SPARC VIS version 3 of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the fused multiply-add instructions, and the Visual Instruction Set (VIS) version 3.0
Accept instructions defined for the sparcfmaf version of the SPARC-V9 ISA, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, and the SPARC64 VI extensions for floating-point multiply-add.
Accept instructions defined for the sparcima version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add.
Accept instructions defined for the sparc4 version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS 2.0, the fused floating-point multiply-add instructions, VIS 3.0, and SPARC4 instructions.
Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the SPARC64 VI extensions for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, and the PAUSE and CBCOND instructions from the SPARC T4 extensions.
Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the SPARC64 VI extensions for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, the VIS3B subset of the VIS 3.0 instructions a subset of the SPARC T3 extensions, called the VIS3B subset of VIS 3.0, and the PAUSE and CBCOND instructions from the SPARC T4 extensions.
Accept instructions defined for the sparc5 version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS 2.0, the fused floating-point multiply-add instructions, VIS 3.0, SPARC4, and SPARC5 instructions.
Accept instructions defined for the sparcace version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add, and SPARCACE instructions.
Accept instructions defined for the sparcaceplus version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add, SPARCACE, and SPARCACEPLUS instructions.
Equivalent to -m64 -xarch=sparc.
Equivalent to -m64 -xarch=sparcvis.
Equivalent to -m64 -xarch=sparcvis2.
Delayed control transfer instruction (DCTI) couples are an undesirable code sequence for the SPARC architecture. –xdecouple=dcti prompts the assembler to insert a no operation (NOP) instruction between the couple. –xdecouple=no%dcti (the default behavior) prevents the assembler from NOP insertion.
Generates additional information for use by the Oracle Developer Studio performance analyzer. If the input file does not contain any stabs (debugging directives), the assembler will generate default stabs needed by the Oracle Developer Studio analyzer. Also see the dbx (1) manual page.
Allow 32-bit addresses in 64-bit mode.
Generate the Hardware Capabilities section. (Default)
Suppress the generation of the Hardware Capabilities section.
Check for address referencing with absolute relocation and issue warning.
Causes the following sections to be removed if they are empty: .bss, .bssf, .lbss, .data, .rodata, .ldata, .lrodata, and .picdata.
When there is a choice between several possible encodings, choose the one that is appropriate for the stated chip. In particular, use the appropriate no-op byte sequence to fill code alignment padding, and warn when instructions not defined for the stated chip are used.
The assembler accepts the instruction sets for the following recognized -xchip values:
generic x86 instruction set
this host processo
Intel Core2 processor
Intel Nehalem processor
AMD Opteron processor
Intel Penryn processor
Intel Pentium architectur
Intel Pentium Pro architecture
Intel Pentium 3 style processor
Intel Pentium 4 style processor
Intel Sandy Bridge processor
Intel Westmere processor
AMD FAM10 processor
Intel Ivy Bridge processor
Intel Haswell processor
For -m64 only, generate R_X86_64_32S relocatable type for data access under kernel. Otherwise, generate R_X86_64_32 under small. SHN_AMD64_LCOMMON and .lbcomm support added under medium. small is the default.
Specify path to the version of cm4defs to use.
fbe normally creates temporary files in the directory /tmp. You may specify another directory by setting the environment variable TMPDIR to your chosen directory. (If TMPDIR is not a valid directory, then fbe will use /tmp).
By default, fbe creates its temporary files in /tmp.
cc (1) , cpp (1) , dbx (1) , ld (1) , m4 (1) , nm (1) , strip (1) , tmpnam (3C) , a.out (4) , attributes (5)
On SPARC platforms, the cpp symbol __sparc is set when the flag -P appears, as well as __sparcv8 with the -m32 flag, and __sparcv9 with the -m64 flag.
On x86/x64, the symbol __i386 is set when the flag -P appears, as well as __amd64 with the -m64 flag.
If the -m (invoke the m4(1) macro processor) option is used, keywords for m4(1) cannot be used as symbols (variables, functions, labels) in the input file since m4(1) cannot determine which keywords are assembler symbols and which keywords are real m4(1) macros.
Whenever possible, you should access the assembler through a compilation system interface program such as the Oracle Developer Studio C compiler, cc (1) , to ensure proper library linking.
All undefined symbols are treated as global.