PowerPC BKI

This section details the state that the CPU should be in for PowerPC BKI acceptance.

For historical reasons, the naming convention for PowerPC BKI constants uses PPC60x, instead of POWERPC. The original PowerPC BKI was written for the PPC60x PowerPC BKI, however all PowerPC processor families (8xx, 8260, 60x) now share the same BKI.

• Register r3 must contain a pointer to the BootConf structure.

• External interrupts must be disabled.

• Instruction and data translations must be disabled.

• Internal (L1) memory cache must be disabled.

• The MMU must be disabled; all MMU's registers and Translation Lookaside Buffer (TLB) entries, if any, must be in a reset/disabled/invalidated state.

• The processor must be in Supervisor privilege state.

• Machine-check exceptions must be enabled.

• The processor must be in a recoverable exception state.

• Floating point instructions must be disabled.

• The kernelSpace field in the BootConf object must point to a description of the initial space that must be established by the microkernel's memory management unit, as described in "The Initial Address Space". The family-dependent part of the tag field of the PhChunk entry is defined as a combination of the following bits:

  • KSP_PPC60x_BAT bit specifies that the mapping must be established using two Block Address Translation (BAT) registers. In this case, the mapping specified by PhChunk (the physical address, the corresponding virtual address and the size) must be properly aligned as required by the PowerPC 60x specifications. The microkernel will establish the required mapping in one data BAT (DBAT) and one instruction BAT (IBAT). Therefore, only four kernelSpace entries can have BAT mappings. If the KSP_PPC60x_BAT bit is not specified, the microkernel uses page address translations to establish the required mapping.

  • KSP_PPC60x_W bit specifies that the write-through memory access attribute must be set in the corresponding BAT or PTEs.

  • KSP_PPC60x_I bit specifies that the caching-inhibited memory access attribute must be set in the corresponding BAT or PTEs.

  • KSP_PPC60x_M bit specifies that the memory coherency memory access attribute must be set in the corresponding BAT or PTEs.

  • KSP_PPC60x_G bit specifies that the guarded memory access attribute must be set in the corresponding BAT or PTEs.

  • KSP_PPC60x_RW bits specify that read and write access are allowed.

  • KSP_PPC60x_RO bits specify that only read access is allowed.