This section details the state that the CPU should be in for the UltraSPARC IIi BKI.
Register I/O must contain a pointer to the BootConf
structure.
Interrupts must be disabled.
Instruction and data caches must be disabled.
At address 0, a minimal trap table must be installed with spill/fill trap handlers.
MMU translation must be enabled.
An initial one-to-one mapping must be built by the boot program. This one-to-one mapping must start at 0 and be large enough to cover all virtual addresses for the memory bank's binary segments. Note that instruction and data Table Look-up Buffers (TLBs) mapped in this way will intially be locked and all TLB entries not included in the initial mapping will be invalid.
The kernelSpace field in the BootConf
object must point to a description of the initial space established
by the microkernel's memory management unit, as described in "The Initial Address Space".
The family-dependent part of the tag field of the PhChunk
entry
is defined as a combination of the following bits:
PhChunk
KSP region typePhChunk Bit | Meaning |
---|---|
KSP_US_TYPE_RAM | one-to-one RAM mapping |
Table 3-3
PHChunk
Data attributesPhChunk Bit | Meaning |
---|---|
KSP_US_ATTR_DG | global |
KSP_US_ATTR_DW | writable |
KSP_US_ATTR_DP | privileged |
KSP_US_ATTR_DE | side effect |
KSP_US_ATTR_DCV | cached virtually |
KSP_US_ATTR_DCP | cached physically (L2-cache) |
KSP_US_ATTR_DIE | inverted endiannes |
KSP_US_ATTR_DNFO | non faulted only |
KSP_US_ATTR_DV | valid |
Table 3-4
PHChunk
Instruction attributesPHChunk Bit | Meaning |
---|---|
KSP_US_ATTR_IG | global |
KSP_US_ATTR_IV | valid |
KSP_US_ATTR_IP | privileged |
KSP_US_ATTR_ICP | cached physically (L2-cache) |
The initial kernel space must at least contain the one-to-one mapping of the available RAM.
The f_bootConf field of the BootConf
structure must point to a processor specific decriptor:
typedef struct usparc_BootConf { VmAddr tlb_lock_start; /* start, size and attributes of the memory */ VmSize tlb_lock_size; /* region locked in I and D TLB by */ int tlb_lock_attr; /* the bootstrap program */ VmAddr trap_table_start; /* address of the trap table */ } usparc_BootConf;
The first three fields decribe the initial one-to-one mapping. The last
one gives the address of the trap table. The SPARC_PROP_I_CACHE
and SPARC_PROP_D_CACHE properties must be present in the
initial device tree. Values for these properties are of the type SparcPropCache
:
typedef struct { uint32_f csize; /* cache size */ uint32_f bsize; /* cache bank size */ uint32_f lsize; /* cache line size */ uint32_f nbanks; /* number of bunks (csize = bsize * nbanks) */ uint32_f type; /* cache type */ } SparcPropCache;