NAME | SYNOPSIS | FEATURES | DESCRIPTION | EXTENDED DESCRIPTION | Allowed Calling Contexts | ATTRIBUTES | SEE ALSO
#include <dki/f_dki.h>void dataCacheFlush(void);
DKI
Provides PowerPC cache management services.
The microkernel provides cache management services, mainly to allow host bus drivers to manage memory coherency for DMA purposes.
Typically, PowerPC family processors have separate instruction and data caches which are virtually indexed and physically tagged. However, the PowerPC architecture does not specify the type or existence of a cache. This allows for various different cache types (unified, or no cache at all). In any case, cache management services should behave consistently. They should do nothing if there is no cache, and data or instruction invalidation routines should be equivalent for a unified cache.
The data cache may operate in either write-through or copy-back mode, on a per line basis, depending on the cached memory attributes. The data/instruction cache size and data/instruction line size are processor implementation specific.
The data/instruction cache configuration is available from the PPC_PROP_CACHE property attached to the NODE_CPU node. (The cpu node may be found in the device tree as a child node of the root node. The cpu node name is NODE_CPU .)
The cache configuration property value is the PpcPropCache structure.
The blockNumber field specifies the number of cache blocks in each data or instruction cache.
The blockSize field specifies the cache block size in bytes.
The blockSizeShift field specifies the number of bits to shift right/left to divide/multiply by the cache block size (cache block size is always a power of 2).
dataCacheFlush globally flushes and invalidates the data cache.
dataCacheBlockFlush flushes and invalidates a given range of addresses within the CPU data cache. The range being flushed is specified by the virtual start address (within the current MMU context) and the range size.
dataCacheInvalidate globally invalidates the data cache. Note that all blocks in the data cache are marked as invalid without writing back any modified lines to memory. This function does nothing if the data cache is disabled.
dataCacheBlockInvalidate invalidates a given range of addresses within the CPU data cache. The range being invalidated is specified by the virtual start address (within the current MMU context) and the range size.
Note that invalidated blocks are not written back to memory. Note also that this service should only be used to invalidate a small memory range; that is, a memory range smaller than the cache size. Otherwise, global invalidation should be used.
instCacheInvalidate globally invalidates the instruction cache; that is, all blocks in the instruction cache are marked as invalid. This function does nothing if the instruction cache is disabled.
instCacheBlockInvalidate invalidates a given range of addresses within the CPU instruction cache. The range being invalidated is specified by the virtual start address (within the current MMU context) and the range size.
Note that this service should only be used to invalidate a small memory range; that is, a memory range smaller than the cache size. Otherwise, global invalidation should be used.
The following table specifies the contexts in which a caller is allowed to invoke each service:
Services | Base level | DKI thread | Interrupt | Blocking |
dataCacheFlush | + | + | + | - |
dataCacheBlockFlush | + | + | + | - |
dataCacheInvalidate | + | + | + | - |
dataCacheBlockInvalidate | + | + | + | - |
instCacheInvalidate | + | + | + | - |
instCacheBlockInvalidate | + | + | + | - |
See attributes(5) for descriptions of the following attributes:
ATTRIBUTE TYPE | ATTRIBUTE VALUE |
---|---|
Interface Stability | Evolving |
NAME | SYNOPSIS | FEATURES | DESCRIPTION | EXTENDED DESCRIPTION | Allowed Calling Contexts | ATTRIBUTES | SEE ALSO