MMU/Cache Configuration

To provide MMU/cache configuration, two new tunables have been added:

• kern.mem.cacheMode

• kern.mem.pgTableSzLog2

kern.mem.cacheMode defines how processor caches should be configured. It is a bit field and is the logical OR of the following bit values:

HID0(ICE)=0x00008000

Instruction cache enabled (L1)

HID0(DCE)=0x00004000

Data cache enabled (L1)

L2CR(L2E)=0x80000000

Unified L2 cache enabled

L2CR(L2DO)=0x00400000

For data access only

L2CR(L2IO)=0x00000400

For instruction access only

L2CR(L2WT)=0x00080000

In write-through mode

kern.mem.pgTableSzLog2 defines the memory size to be allocated to the MMU hardware page table (HTAB). To force the HTAB table size to be a power of 2, the tunable value is defined as Log2(size). Thus, 2^kern.mem.pgTableSzLog2 bytes are allocated to the HTAB table. kern.mem.pgTableSzLog2 must be in the value range [16..25].

This support applies to the PowerPC platform only.