ChorusOS 5.0 Transition Guide

Watchdog Timer DDI

The new watchdog timer is essentially a counter driven by a clock signal. The watchdog timer DDI provides a countdown register, which is the main timer. This register is decremented at each clock tick. Its initial value is set through the limit register, either at initialization time, or at pat time.

If the countdown register reaches zero, a signal is alerted to produce a specified effect (hard reset, soft reset or interrupt). Depending on the type of watchdog device, it is possible to "pat" the timer to avoid this effect. This "patting" of the timer must occur at regular intervals.

The watchdog timer device may operate in two separate modes:

When operating in the reset mode, the watchdog device asserts a board reset signal if a watchdog timeout occurs. When operating in interrupt mode, the watchdog device asserts an interrupt line if a watchdog timeout occurs. The watchdog timer driver interface allows the watchdog device to operate in any mode.

For more information on how the watchdog timer is implemented in ChorusOS 5.0, refer to "Analyzing System Failure: Black Boxes, Watchdog Timers and Logging" in the ChorusOS 5.0 Application Developer's Guide and to the wdtimer(9DDI) man page.