ChorusOS man pages section 9DKI: Driver to Kernel Interface

icacheLineInval_usparc(9DKI)

NAME

icacheInval_usparc, icacheLineInval_usparc, icacheBlockInval_usparc, dcacheFlush_usparc, dcacheLineFlush_usparc, dcacheBlockFlush_usparc- UltraSPARC cache management

SYNOPSIS

 #include <dki/f_dki.h>

addr

size

addr

size

API RESTRICTIONS

The function or functions documented here may not be used safely in all application contexts with all APIs provided in the ChorusOS 5.0 product.

See API(5FEA) for details.

FEATURES

DKI

DESCRIPTION

The microkernel provides cache management services, mainly to allow host bus drivers to manage memory coherency for DMA purposes.

EXTENDED DESCRIPTION

family processors have split instruction and data caches, which are directly mapped and virtually indexed. The instruction cache is two-way associative, directly mapped. It is composed of two banks with an LRU replacement mechanism. The data cache is one-way associative, directly mapped and operates in the write-through mode.

The data and instruction caches configuration is available as i-cache and d-cache properties attached to the CPU node, which is named cpu . The CPU node may be found in the device tree as a child node of the root node.

The cache configuration property value is the SparcPropCache structure shown below.

typedef struct {

    uint32_f  csize;   /* cache size */
    uint32_f  bsize;   /* cache bank size */
    uint32_f  lsize;   /* cache line size */
    uint32_f  nbanks;  /* number of bunks (csize = bsize * nbanks) */
    uint32_f  type;    /* cache type */

} SparcPropCache;

The csize field specifies the cache size in bytes.

The bsize field specifies the cache bank size in bytes.

The lsize field specifies the cache line size in bytes.

The nbanks field specifies the number of banks.

The type field specifies the cache properties. It is composed of the following bit-fields and flags:

CACHE_TYPE_IDX

Bit-field specifying the cache indexing mode:

CACHE_TYPE_IDX_PHYS -- physically indexed

CACHE_TYPE_IDX_VIRT -- virtually indexed

CACHE_TYPE_TAG

Bit-field specifying the cache tagging mode:

CACHE_TYPE_TAG_PHYS -- physically tagged

CACHE_TYPE_TAG_VIRT -- virtually tagged

CACHE_TYPE_MODE

Bit-field specifying the data cache mode:

CACHE_TYPE_MODE_WT -- write-through mode

CACHE_TYPE_MODE_CB -- copy-back mode

CACHE_TYPE_CFS

Flag specifying that the entire cache flush/invalidation is supported.

CACHE_TYPE_LFS

Flag specifying that line cache flush/invalidation is supported.

CACHE_TYPE_MATCH

Flag specifying that the tag match criteria is used for the line flush/invalidation

Note -

Typically, a host bus driver does not need to examine the caches properties because they are already taken into account by the cache management service routines described below.

icacheInval() invalidates the entire CPU Instruction Cache.

icacheLineInval() invalidates a given cache line within the CPU Instruction Cache. The cache line is specified by a virtual address.

icacheBlockInval() invalidates a given range within the CPU Instruction Cache. The range is specified by the virtual start address and range size.

dcacheFlush() flushes and invalidates the entire CPU Data Cache.

dcacheLineFlush() flushes and invalidates a given cache line within the CPU Data Cache. The cache line is specified by a virtual address.

ALLOWED CALLING CONTEXTS

The following table specifies the contexts in which a caller is allowed to invoke each service:

Services	Base level	DKI thread	Interrupt	Blocking
`icacheInval()`	+	+	+	-
`icacheLineInval()`	+	+	+	-
icacheBlockInval	+	+	+	-
dcacheFlush	+	+	+	-
dcacheLineFlush	+	+	+	-
dcacheBlockFlush	+	+	+	-

ATTRIBUTES

See attributes(5) for descriptions of the following attributes:

ATTRIBUTE TYPE	ATTRIBUTE VALUE
Interface Stability	Evolving