Trapping the FPE Signal

Often programmers working with code that requires floating point calculations want to debug exceptions generated in a program. When a floating point exception like overflow or divide by zero occurs, the system returns a reasonable answer as the result for the operation that caused the exception. Returning a reasonable answer allows the program to continue executing quietly. Solaris implements the IEEE Standard for Binary Floating Point Arithmetic definitions of reasonable answers for exceptions.

Since a reasonable answer for floating point exceptions is returned, exceptions do not automatically trigger the signal SIGFPE.

To find the cause of an exception, you need to set up a trap handler in the program so that the exception triggers the signal SIGFPE. (See ieee_handler(3m) man page for an example of a trap handler.)

You can enable a trap using:

• ieee_handler

• fpsetmask (see the fpsetmask(3c) man page)

• -ftrap compiler flag (for FORTRAN 77 and Fortran 90, see the f77(1) and f90(1) man pages)

When you set up a trap handler using ieee_handler , the trap enable mask in the hardware floating point status register is set. This trap enable mask causes the exception to raise SIGFPE at run time.

Once you have compiled the program with the trap handler, load the program into dbx. Before you can catch the SIGFPE, you must add FPE to the dbx signal catch list, using the command:

---

(dbx) catch FPE

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By default, FPE is on the ignore list.

Determining Where the Exception Occurred

After adding FPE to the catch list, run the program in dbx. When the exception you are trapping occurs, SIGFPE is raised and dbx stops the program. Now you can trace the call stack using the dbx where command to help find the specific line number of the program where the exception occurs.

Determining the Cause of the Exception

To determine the cause of the exception, use the regs -f command to display the floating point state register (FSR). Look at the accrued exception (aexc) and current exception (cexc) fields of the register, which contain bits for the following floating-point exception conditions:

• Invalid operand

• Overflow

• Underflow

• Division by zero

• Inexact result

For more information on the floating point state register, see Version 8 (for V8) or Version 9 (for V9) of The SPARC Architecture Manual.For more discussion and examples, see the floating point manual, Numerical Computation Guide.