Glossary |
Used on slot 0 and slot 1 boards to implement the on-board system address bus. Connects four CPUs (or two I/O controllers) to the address controller on the expander board.
automatic system recovery (ASR)
The ability of a system to recover automatically in the event of a hardware failure. Identifies and isolates a failing hardware component, and builds a bootable system configuration without the failed hardware component.
The combination of an expander board, a slot 0 board, and a slot 1 board.
boot bus controller (SBBC) ASIC
Used on slot 0 and slot 1 boards to provide a console-bus-slave interface to PROM bus, JTAG, and I2C devices for board initialization. When used with CPUs, provides a boot-bus path to POST code.
Coherency directory cache inside the system address controller (AXQ) ASIC. Caches recent memory tag states stored in the ECC bits of memory to speed up accesses to cache lines on other board sets.
The ability to service various parts of a machine without interfering with a running system.
Connects into one of two control slots on the Sun Fireplane interconnect. Consists of a centerplane support board, a System Control board, and a peripheral board.
A slot 0 board that holds four CPUs, each of which controls eight DIMMs. The CPU/Memory board has an off-board bandwidth of 4.8 Gbyte/sec.
Used on the Sun Fireplane interconnect to control the 18x18 data crossbar.
An 18x18 data crossbar that connects the system data interfaces on each expander board to the Sun Fireplane interconnect.
data path controller (SDC) ASIC
Used on the slot 0 and slot 1 boards to controls the on-board system data path. Repeats the console bus to the two on-board boot-bus controllers.
Used on the slot 0 and slot 1 boards to connect the on-board system data path to the off-board system data path.
A dual-CPU data switch ASIC that connects two CPUs and two memory units to the data switch ASIC.
The combination of an SRD and its client domains.
Error isolation between client domains.
The process of activating or deactivating devices such as boards and power supplies in a running Solaris operating system while user applications continue.
A board connecting into the Sun Fireplane interconnect at the slot 0 and slot 1 sockets.
Gigabyte per second of capacity = 230 = 1,073,741,824 bytes
An active device that can be installed and removed from a running system for dynamic reconfiguration.
An assembly that holds one 33-MHz standard PCI card and three 33/66 MHz standard PCI cards. The PCI cards can be hot-swapped from the I/O slot while the system is in operation for dynamic reconfiguration.
An assembly that holds one 33-MHz standard PCI card and three 33/66/90 MHz standard PCI cards. The PCI cards can be hot-swapped from the I/O slot while the system is in operation for dynamic reconfiguration.
Joint Test Action Group. An IEEE standard (1149.1) for serial scanning of chip internal registers.
The time for a single data item to be delivered from memory to a CPU.
A linked domain is when a domain is removed from an inter-domain network.
Megabyte of capacity = 220 = 1,048,576 bytes.
Used on the hsPCI-x and hsPCI+ boards and the link board to connect the system interconnect to the PCI buses.
A passive hot-swap carrier that adapts standard PCI pins to connectors.
The hardware components powered by a group of power supplies.
A recordstop is a nonfatal error such as correctable single-bit errors in a data path.
response multiplexer (RMX) ASIC
An 18x18 crossbar that transmits transaction responses and connects together the address controllers on each expander board.
A mode of the system interconnect that enables multiple snoopy coherence domains to be connected together.
Two system boards in a board set that are in separate domains.
Address bus containing a maximum snoop rate of 150 million snoops per second or a 9.6-Gbyte/sec data rate.
The interconnect architecture used by the UltraSPARC IV Cu generation of CPUs. This architecture is the physical active-logic centerplane that implements the system address and data crossbars.
Sun Fireplane interconnect architecture
The cache-coherency protocol and set of address transactions that are used by all UltraSPARC IV Cu CPU-based systems.
Sun Fireplane interconnect data path
The point-to-point data protocol used between the DCDS and DX ASICs.
system address controller
(AXQ) ASIC
Connects the address repeaters on the slot 0 and the slot 1 boards to the Sun Fireplane interconnect address and response crossbars. Used on expander boards.
Connects into one of 18 system slots in the Sun Fireplane interconnect with the expander board. Contains slot 0 boards and slot 1 boards.
Connects into one of two system control slots in the Sun Fireplane interconnect with the centerplane support board. This board set contains the System Control board and a system control peripheral board ( DVD-ROM, DAT drive, hard drive).
system data interface (SDI) ASIC
Used on the expander boards to connect the data switches on the slot 0 and the slot 1 boards to the Sun Fireplane interconnect data crossbars.
The UltraSPARC IV Cu CPU is used on the CPU/Memory board.
Removing a domain from the inter-domain network.
Copyright © 2006, Sun Microsystems, Inc. All Rights Reserved.