Level 1 Data Cache Test (l1dcachetest)
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l1dcachetest exercises the level1 Data cache in the CPU module of Sun systems. The test writes, reads, and verifies access of multiple virtual addresses. The virtual addresses are so chosen that they cause targeted hits and misses in the cache. The test dynamically determines the size and organization of the cache and tunes the test accordingly to be effective on the l1dcache.
l1dcachetest provides data path testing of on-chip buses. With rapid move to deep sub-micron (DSM) designs, GHz clock frequencies, feature size process of 0.18 micron and below, ensuring the integrity of signals as they traverse conductors on a chip is becoming challenge. l1dcachetest subtests induce crosstalk noise in on-chip data buses by using Maximum Aggressor Fault (MAF) models.
l1dcahetest is self scaling and adaptive. It scales with the size of system. l1dcachetest is mult-threaded. Although, selection of CPU IDs, is kept as one of the options but if its not specified, it automatically retrieves the number of CPUs in the system and internally creates that many threads of l1dcachetest to give coverage to the whole system at a given time. The test also determines the sizes and organization of l1cache.
l1dcachetest Options
To reach the dialog box below, right-click on the test name in the System Map and select Test Parameter Options. If you do not see this test in the System Map, you might need to expand the collapsed groups, or your system may not include the device appropriate to this test. Refer to the SunVTS User's Guide for more details.
FIGURE 18-1 l1dcachetest Test Parameter Options Dialog Box
TABLE 18-1 l1dcachetest Options
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Option
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Description
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Processors
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This option can be used to select the CPU IDs for which to run this test. The test will use all CPUs on the system by default. Hence this parameter is optional.
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Thrash Cycles
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Specifies the number of iteration for data cache subtests. The default is 256.
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PCLoop
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Specifies the number of iteration for Prefetch Cache Subtests. The default is 256. (NOTE : This option will only be displayed on system with UltraSPARC-III and UltraSPARC-IV family of processors.
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ECC Error
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Specifies whether the error messaging should be on or off. The error monitor monitors the /var/adm/messages file for failure messages which could be caused during test. The default is OFF.
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ECC Threshold
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Specifies the threshold value of the number of errors after which the test would register an error. This argument is only applicable, if the Error Monitor is on. The errors that come on the /var/adm/messages could be correctable errors, that is why the threshold value is provided to give facility to ignore the errors if they are below the threshold value. The default value is 1.
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Performance Counters
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Enables or Diables the Performance counter measurements related to Data Cache and Prefetch Cache events. By Default, it is OFF.
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Note - Only one l1dcachetest will be registered for all the CPUs in the system.The l1dcachetest is automatically bound to a processor. Users are advised to not use the Processor Affinity option for the l1dcachetest.
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l1dcachetest Test Modes
TABLE 18-2 l1dcachetest Supported Test Modes
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Test Mode
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Description
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Connection
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Performs the Connection subtest.
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Exclusive
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Performs only the l1dcachetest (full test).
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l1dcachetest Command-Line Syntax
/opt/SUNWvts/bin/l1dcachetest standard_arguments -o [
[ M=1+2+3... ],[ count=number ], [ pcloop=number ], [em=Enabled|Disabled], [threshold=1,255], [perf=Enabled|Disabled], [dev=l1cache] ]
TABLE 18-3 l1dcachetest Command-Line Syntax
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Argument
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Description
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M=1+2+3...
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This option can be used to select the CPU IDs for which to run this test. The test will use all CPUs on the system by default. Hence this parameter is optional. The CPU IDs currently present in the system can be retrieved with psrinfo(1M) command. Specifying a CPU ID not present in the system or one which is currently offline induces an appropriate error messages from the test. Example: If you want to select CPU IDs 4, 5, 6, and 7 , specify : M=4+5+6+7
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count=number
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Specifies the number of iteration for Data Cache Subtests. The default is 256.
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pcloop=number
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Specifies the number of iteration for Prefetch Cache Subtests. The default is 256. (NOTE : This option s only for system with UltraSPARC-III and UltraSPARC-IV family of processors. For others, it will ignored.
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em=Enabled|Disabled
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Specifies whether the error messaging should be on or off.The error monitor monitors the /var/adm/messages file for failure messages which could be caused during test. The default is OFF.
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threshold=1,255
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Specifies the threshold value of the number of errors after which the test would register an error. This argument is only applicable, if the Error Monitor is on. The errors that come on the /var/adm/messages could be correctable error, that is why threshold value is provided for the user to give facility to ignore the errors if they are below thrshold value. The default value is 1. If set to zero, the test will still report errors but will not stop.
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perf=Enabled|Disabled
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Enables or Diables the Performance counter measurements related to Data Cache and Prefetch Cache events. By Default, it is OFF.
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dev=l1cache
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Specifies the device. The default is l1cache.
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Note - If you do not mention the value for count or pcloop, the test will run with the default value of count and pcloop. To disable Data Cache subtests, specify count=0, and for Prefetch Catch subtests, specify pcloop=0.
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Note - Command line syntax still supports old command line syntax, but this will not be supported in a fulure release of SunVTS.
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64-bit tests are located in the sparcv9 subdirectory: /opt/SUNWvts/bin/sparcv9/testname. If a test is not present in this directory, then it may only be available as a 32-bit test. For more information refer to "32-Bit and 64-Bit Tests section of the SunVTS Test Reference Manual.
| SunVTS 5.1 Patch Set 6 Documentation Supplement
| 817-6318-10
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Copyright © 2004, Sun Microsystems, Inc. All rights reserved.