C H A P T E R 22 |
Level 2 Cache Test (l2sramtest) |
l2sramtest exercises the level2 cache in the CPU module of Sun systems. In most CPUs, the level2 cache is also the external cache, but in some cases the level2 cache is on the chip. This test writes, reads, and verifies access of multiple virtual addresses. This test contains multiple subtests that try to exercise the l2cache by causing hits/misses, performing marching patterns on the l2cache cells, and writing patterns that cause electrical stress.
l2sramtest is self scaling and adaptive. It scales with the size of the system. It will automatically retrieve the number of CPUs in the system and internally create that many threads of l2sramtest to give coverage to the whole system at a given time. This test also dynamically determines the size and organization of the l2cache. The user does not have to input these values.
To reach the dialog box below, right-click on the test name in the System Map and select Test Parameter Options. If you do not see this test in the System Map, you might need to expand the collapsed groups, or your system may not include the device appropriate to this test. Refer to the SunVTS User's Guide for more details.
Note - The l2sramtest automatically handles processor binding. Users are advised to not use the Processor Affinity option for the l2sramtest. |
/opt/SUNWvts/bin/sparcv9/l2sramtest -standard_arguments -o [dev=l2sram, count=[1...1023], em=[Enabled,Disabled], threshold=[0..255]]
Note - The l2sramtest is not a per CPU test. There will be only one l2sramtest for the whole system (one image of Solaris). It will run on all the CPUs of the domain. |
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