Defines cache properties for use by the optimizer. This option does not guarantee that any particular cache property is used.
Although this option can be used alone, it is part of the expansion of the -xtarget option; its primary use is to override a value supplied by the -xtarget option.
This release introduces an optional property [/ti] which sets the number of threads that can share the cache. If you do not specify a value for t, the default is 1.
c must be one of the following:
generic
native
s1/l1/a1[/t1]
s1/l1/a1[/t1]:s2/l2/a2[/t2]
s1/l1/a1[/t1]:s2/l2/a2[/t2]:s3/l3/a3[/t3]
The s/l/a/t properties are defined as follows:
si |
The size of the data cache at level i, in kilobytes |
li |
The line size of the data cache at level i, in bytes |
ai |
The associativity of the data cache at level i |
ti |
The number of hardware threads sharing the cache at level i |
The following table lists the-xcache values.
Table B–16 The -xcache Flags
Flag |
Meaning |
---|---|
generic |
This is the default value which directs the compiler to use cache properties for good performance on most x86 and SPARC processors, without major performance degradation on any of them. With each new release, these best timing properties will be adjusted, if appropriate. |
native |
Set the parameters for the best performance on the host environment. |
s1/l1/a1[/t1] |
Define level 1 cache properties. |
s1/l1/a1[/t1]:s2/l2/a2[/t2] |
Define levels 1 and 2 cache properties. |
s1/l1/a1[/t1]:s2/l2/a2[/t2]:s3/l3/a3[/t3] |
Define levels 1, 2, and 3 cache properties. |
Example:-xcache=16/32/4:1024/32/1 specifies the following:
Level 1 cache has: 16K bytes 32 bytes line size 4-way associativity |
Level 2 cache has: 1024K bytes 32 bytes line size Direct mapping associativity |