SPARC Assembly Language Reference Manual

E.4 SPARC-V9 Floating-Point Instruction Set Mapping

SPARC-V9 floating-point instructions are shown in the following table.

Table E–11

SPARC 

Mnemonic [Types of Operands are denoted by the following lower-case letters:i 32-bit integerx 64-bit integers singled doubleq quad]

Argument List 

Description 

F[sdq]TOx

fstox

fdtox

fqtox

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert floating point to 64-bit integer  

 

fstoi

fdtoi

fqtoi

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert floating-point to 32-bit integer 

FxTO[sdq]

fxtos

fxtod

fxtoq

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert 64-bit integer to floating point  

 

fitos

fitod

fitoq

fregrs2, fregrd

fregrs2, fregrd

fregrs2, fregrd

Convert 32-bit integer to floating point 

FMOV[dq]

fmovd

fmovq

fregrs2, fregrd

fregrs2, fregrd

Move double  

Move quad 

FNEG[dq]

fnegd

fnegq

fregrs2, fregrd

fregrs2, fregrd

Negate double  

Negate quad 

FABS[dq]

fabsd

fabsq

fregrs2, fregrd

fregrs2, fregrd

Absolute value double  

Absolute value quad 

LDFA

 

LDDFA

 

LDQFA

lda

lda

ldda

ldda

ldqa

ldqa

[regaddr] imm_asi, fregrd

[reg_plus_imm] %asi, fregrd

[regaddr] imm_asi, fregrd

[reg_plus_imm] %asi, fregrd

[regaddr] imm_asi, fregrd

[reg_plus_imm] %asi, fregrd

Load floating-point register from alternate space  

Load double floating-point register from alternate space.  

Load quad floating-point register from alternate space 

STFA

 

STDFA

 

STQFA

sta

sta

stda

stda

stqa

stqa

fregrd, [regaddr] imm_asi

fregrd, [reg_plus_imm] %asi

fregrd, [regaddr] imm_asi

fregrd, [reg_plus_imm] %asi

fregrd, [regaddr] imm_asi

fregrd, [reg_plus_imm] %asi

Store floating-point register to alternate space  

Store double floating-point register to alternate space 

Store quad floating-point register to alternate space