E.6.7 Memory Access Instructions

These memory access instructions are part of the SPARC-V9 instruction set extensions.

Table E–24


SPARC	imm_asi	Argument List	Description
`STDFA` `STDFA` `STDFA` `STDFA`	`ASI_PST8_P` `ASI_PST8_S` `ASI_PST8_PL` `ASI_PST8_SL`	stda freg_rd, [freg_rs1] reg_mask, imm_asi	eight 8-bit conditional stores to: primary address space secondary address space primary address space, little endian secondary address space, little endian
`STDFA` `STDFA` `STDFA` `STDFA`	`ASI_PST16_P` `ASI_PST16_S` `ASI_PST16_PL` `ASI_PST16_SL`		four 16-bit conditional stores to: primary address space secondary address space primary address space, little endian secondary address space, little endian
`STDFA` `STDFA` `STDFA` `STDFA`	`ASI_PST32_P` `ASI_PST32_S` `ASI_PST32_PL` `ASI_PST32_SL`		two 32-bit conditional stores to: primary address space secondary address space primary address space, little endian secondary address space, little endian

Note –

To select a partial store instruction, use one of the partial store ASIs with the STDA instruction.

Table E–25


SPARC	imm_asi	Argument List	Description
`LDDFA` `STDFA`	`ASI_FL8_P`	ldda [reg_addr] imm_asi, freq_rd stda freq_rd, [reg_addr] imm_asi	8-bit load/store from/to: primary address space
`LDDFA` `STDFA`	`ASI_FL8_S`	ldda [reg_plus_imm] %asi, freq_rd stda [reg_plus_imm] %asi	secondary address space
`LDDFA` `STDFA`	`ASI_FL8_PL`		primary address space, little endian
`LDDFA` `STDFA`	`ASI_FL8_SL`		secondary address space, little endian
`LDDFA` `STDFA`	`ASI_FL16_P`		16-bit load/store from/to: primary address space
`LDDFA` `STDFA`	`ASI_FL16_S`		secondary address space
`LDDFA` `STDFA`	`ASI_FL16_PL`		primary address space, little endian
`LDDFA` `STDFA`	`ASI_FL16_SL`		secondary address space, little endian

Note –

To select a short floating-point load and store instruction, use one of the short ASIs with the LDDA and STDA instructions.

Table E–26


SPARC	imm_asi	Argument List	Description
`LDDA` `LDDA`	`ASI_NUCLEUS_QUAD_LDD` `ASI_NUCLEUS_QUAD_LDD_L`	[reg_addr] imm_asi, reg_rd [reg_plus_imm] %asi, reg_rd	128-bit atomic load 128-bit atomic load, little endian
`LDDFA` `STDFA`	`ASI_BLK_AIUP`	ldda [reg_addr] imm_asi, freq_rd stda freq_rd, [reg_addr] imm_asi	64-byte block load/store from/to: primary address space, user privilege
`LDDFA` `STDFA`	`ASI_BLK_AIUS`	ldda [reg_plus_imm] %asi, freq_rd stda freg_rd, [reg_plus_imm] %asi	secondary address space, user privilege.
`LDDFA` `STDFA`	`ASI_BLK_AIUPL`		primary address space, user privilege, little endian
`LDDFA` `STDFA`	`ASI_BLK_AIUSL`		secondary address space, user privilege little endian
`LDDFA` `STDFA`	`ASI_BLK_P`		primary address space
`LDDFA` `STDFA`	`ASI_BLK_S`		secondary address space
`LDDFA` `STDFA`	`ASI_BLK_PL`		primary address space, little endian
`LDDFA` `STDFA`	`ASI_BLK_SL`		secondary address space, little endian
`LDDFA` `STDFA`	`ASI_BLK_COMMIT_P`		64-byte block commit store to primary address space
`LDDFA` `STDFA`	`ASI_BLK_COMMIT_S`		64-byte block commit store to secondary address space

Note –

To select a block load and store instruction, use one of the block transfer ASIs with the LDDA and STDA instructions.