SPARC Assembly Language Reference Manual

E.2.1 Extended Instruction Definitions to Support the 64-bit Model

Table E–5

FCMP, FCMPE 

Floating-Point Compare—can set any of the four floating-point condition codes. 

LDFSR, STFSR 

Load/Store FSR- only affect low-order 32 bits of FSR 

LDUW, LDUWA 

Same as LD, LDA in SPARC-V8 

RDASR/WRASR 

Read/Write State Registers - access additional registers 

SAVE/RESTORE 

 

SETHI 

 

SRA, SRL, SLL, Shifts 

Split into 32-bit and 64-bit versions 

Tcc 

(was Ticc) Operates with either the 32-bit integer condition codes (icc), or the 64-bit integer condition codes (xcc) 

All other arithmetic operations operate on 64-bit operands and produce 64-bit results.