Front and Rear Panel Components
Plan Communication With the Server Module During Installation
Optional Component Installation
Modular System Chassis Preparation
Insert the Server Module Into the Chassis
Communicating With the Server Module During Startup
Monitor the Diagnostic Messages
Powering On the Server Module for the First Time
Initial Power-On Task Overview
Power On the System for the First Time
Install Oracle Solaris Software From the Network
Oracle Solaris Configuration Settings
Assign a Static IP Address to the Service Processor
Understanding System Administration Resources
Platform-Specific Oracle ILOM Features
Oracle VM Server for SPARC Overview
Hardware Management Pack Overview
Source for Downloading Hardware Management Pack Software
Hardware Management Pack Documentation
Display the Oracle ILOM -> Prompt
Reset the Server From the Oracle Solaris OS
Reset the Server From Oracle ILOM
Reset the SP to Default Values
Important Hardware RAID Guidelines
Disk Zones for SPARC T3-1 Servers With Sixteen-Disk Backplanes
Displaying Disk Zone Information
Enabling and Disabling Disk Zoning In the Field
Prepare to Use the FCode Utility
Hot Spare Drives in RAID Volumes (LSI)
Determining If a Drive Has Failed
RAID Drive Replacement Strategies
Changing Server Identification Information
Change Customer FRUdata Information
Change System Identifier Information
Restore Host Power State at Restart
Specify Host Power State at Restart
Disable or Re-Enable Power-On Delay
Specify Parallel Boot of the SP and Host
Configure Host Behavior With the Keyswitch State
Disable or Re-Enable Network Access to the SP
Display the DHCP Server IP Address
Using an In-band Connection to the SP
Configure the Host Boot Mode of Oracle VM Server for SPARC
Change the Host Boot Mode Behavior at Reset
Manage the Host Boot Mode Script
Display Host Boot Mode Expiration Date
Override OpenBoot PROM Settings to Reset the Server
Configuring Server Behavior at Restart
Specify Behavior When the Host Resets
Specify Behavior When the Host Stops Running
Specify Behavior at Boot Timeout
Specify Behavior if Restart Fails
Specify Maximum Restart Attempts
Enabling Automatic System Recovery
Identifying WWN-Designated SAS2 Devices
probe-scsi-all Output Example (SPARC T3-1, Eight-Disk Backplane)
probe-scsi-all Output Example (SPARC T3-1, Sixteen-Disk Backplane)
probe-scsi-all Output Example (SPARC T3-4)
Identify a Disk Slot Using probe-scsi-all (OBP)
Identify a Disk Slot Using prtconf (Oracle Solaris, Onboard Controllers)
Identify a Disk Slot Using prtconf (Oracle Solaris, Single Initiator)
WWN Syntax in an OS Installation on a Specific Device
WWN Syntax in an OS Installation on a RAID Volume
Front and Rear Panel Components
Oracle ILOM Troubleshooting Overview
Display FRU Information (show Command)
Check for Faults (show faulty Command)
Check for Faults (fmadm faulty Command)
Clear Faults (clear_fault_action Property)
Service-Related Oracle ILOM Command Summary
Interpreting Log Files and System Messages
Check the Message Buffer (dmesg Command)
View the System Message Log Files
List FRU Status (prtdiag Command)
Managing Faults (Oracle Solaris PSH)
Oracle Solaris PSH Technology Overview
Oracle ILOM Properties That Affect POST Behavior
Managing Components (ASR Commands)
Checking if Oracle VTS Software Is Installed
Check if Oracle VTS Software Is Installed
Find the Modular System Serial Number
Find the Server Module Serial Number
Removing the Server Module From the Modular System for Service
Clear the Fault and Verify the Functionality of the Replacement DIMM
Servicing a Service Processor Card
Remove the Service Processor Card
Install the Service Processor Card
Replacing the Server Module Enclosure Assembly
Transfer Components to Another Enclosure Assembly
Returning the Server Module to Operation
POST error messages use the following syntax:
c:s > ERROR: TEST = failing-test c:s > H/W under test = FRU c:s > Repair Instructions: Replace items in order listed by H/W under test above c:s > MSG = test-error-message c:s > END_ERROR
In this syntax, c = the core number, s = the strand number.
Warning messages use the following syntax:
WARNING: message
Informational messages use the following syntax:
INFO: message
In the following example, POST reports an uncorrectable memory error affecting DIMM locations /SYS/MB/CMP0/BOB0/CH0/D0 and /SYS/MB/CMP0/BOB1/CH0/D0. The error was detected by POST running on node 0, core 7, strand 2.
2010-07-03 18:44:13.359 0:7:2>Decode of Disrupting Error Status Reg (DESR HW Corrected) bits 00300000.00000000 2010-07-03 18:44:13.517 0:7:2> 1 DESR_SOCSRE: SOC (non-local) sw_recoverable_error. 2010-07-03 18:44:13.638 0:7:2> 1 DESR_SOCHCCE: SOC (non-local) hw_corrected_and_cleared_error. 2010-07-03 18:44:13.773 0:7:2> 2010-07-03 18:44:13.836 0:7:2>Decode of NCU Error Status Reg bits 00000000.22000000 2010-07-03 18:44:13.958 0:7:2> 1 NESR_MCU1SRE: MCU1 issued a Software Recoverable Error Request 2010-07-03 18:44:14.095 0:7:2> 1 NESR_MCU1HCCE: MCU1 issued a Hardware Corrected-and-Cleared Error Request 2010-07-03 18:44:14.248 0:7:2> 2010-07-03 18:44:14.296 0:7:2>Decode of Mem Error Status Reg Branch 1 bits 33044000.00000000 2010-07-03 18:44:14.427 0:7:2> 1 MEU 61 R/W1C Set to 1 on an UE if VEU = 1, or VEF = 1, or higher priority error in same cycle. 2010-07-03 18:44:14.614 0:7:2> 1 MEC 60 R/W1C Set to 1 on a CE if VEC = 1, or VEU = 1, or VEF = 1, or another error in same cycle. 2010-07-03 18:44:14.804 0:7:2> 1 VEU 57 R/W1C Set to 1 on an UE, if VEF = 0 and no fatal error is detected in same cycle. 2010-07-03 18:44:14.983 0:7:2> 1 VEC 56 R/W1C Set to 1 on a CE, if VEF = VEU = 0 and no fatal or UE is detected in same cycle. 2010-07-03 18:44:15.169 0:7:2> 1 DAU 50 R/W1C Set to 1 if the error was a DRAM access UE. 2010-07-03 18:44:15.304 0:7:2> 1 DAC 46 R/W1C Set to 1 if the error was a DRAM access CE. 2010-07-03 18:44:15.440 0:7:2> 2010-07-03 18:44:15.486 0:7:2> DRAM Error Address Reg for Branch 1 = 00000034.8647d2e0 2010-07-03 18:44:15.614 0:7:2> Physical Address is 00000005.d21bc0c0 2010-07-03 18:44:15.715 0:7:2> DRAM Error Location Reg for Branch 1 = 00000000.00000800 2010-07-03 18:44:15.842 0:7:2> DRAM Error Syndrome Reg for Branch 1 = dd1676ac.8c18c045 2010-07-03 18:44:15.967 0:7:2> DRAM Error Retry Reg for Branch 1 = 00000000.00000004 2010-07-03 18:44:16.086 0:7:2> DRAM Error RetrySyndrome 1 Reg for Branch 1 = a8a5f81e.f6411b5a 2010-07-03 18:44:16.218 0:7:2> DRAM Error Retry Syndrome 2 Reg for Branch 1 = a8a5f81e.f6411b5a 2010-07-03 18:44:16.351 0:7:2> DRAM Failover Location 0 for Branch 1 = 00000000.00000000 2010-07-03 18:44:16.475 0:7:2> DRAM Failover Location 1 for Branch 1 = 00000000.00000000 2010-07-03 18:44:16.604 0:7:2> 2010-07-03 18:44:16.648 0:7:2>ERROR: POST terminated prematurely. Not all system components tested. 2010-07-03 18:44:16.786 0:7:2>POST: Return to VBSC 2010-07-03 18:44:16.795 0:7:2>ERROR: 2010-07-03 18:44:16.839 0:7:2> POST toplevel status has the following failures: 2010-07-03 18:44:16.952 0:7:2> Node 0 ------------------------------- 2010-07-03 18:44:17.051 0:7:2> /SYS/MB/CMP0/BOB0/CH1/D0 (J1001) 2010-07-03 18:44:17.145 0:7:2> /SYS/MB/CMP0/BOB1/CH1/D0 (J3001) 2010-07-03 18:44:17.241 0:7:2>END_ERROR