wbinvd
Write back and invalidate the cache.
wbinvd
invd
Invalidate the entire cache.
invd
invlpg mem32
Invalidate a single entry in the translation lookaside buffer.
invlpg 5(%ebx)
lock
LOCK# -> NEXT Instruction
The LOCK # signal is asserted during execution of the instruction following the lock prefix. This signal can be used in a multiprocessor system to ensure exclusive use of shared memory while LOCK # is asserted. The bts instruction is the read-modify-write sequence used to implement test-and-run.
The lock prefix works only with the instructions listed here. If a lock prefix is used with any other instructions, an undefined opcode trap is generated.
bt, bts, btr, btc |
m, r/imm |
xchg |
r, m |
xchg |
m, r |
add, or, adc, sbb, and, sub, xor |
m, r/imm |
not, neg, inc, dec |
m |
Memory field alignment does not affect the integrity of lock.
If a different 80386 processor is concurrently executing an instruction that has a characteristic listed here, locked access is not guaranteed. The previous instruction:
Does not follow a lock prefix
Is not on the previous list of acceptable instructions
A memory operand specified has a partial overlap with the destination operand.
lock
nop
NO OPERATION
No operations are performed by nop. The xchgl %eax, %eax instruction is an alias for the nop instruction.
nop
hlt Address Prefix addr16 Data Prefix data16
HLT -> ENTER HALT STATE
halt puts the 80386 in a HALT state by stopping instruction execution. Execution is resumed by an nmi or an enabled interrupt. After a halt, if an interrupt is used to continue execution, the saved CS:EIP or CS:IP value points to the next instruction (after the halt).
The halt instruction is privileged.
hlt