Shift (sal, shl, sar, shr)

shl{bwl} %cl, r/m[8|16|32] sar{bwl} imm8, r/m[8|16|32] sar{bwl} %cl, r/m[8|16|32] shr{bwl} imm8, r/m[8|16|32]

sal{bwl} 	%cl, r/m[8|16|32]
shl{bwl} 	imm8, r/m[8|16|32]
sal{bwl} 	imm8, r/m[8|16|32]
shr{bwl} 	%cl, r/m[8|16|32]

Operation

shift-left r/m[8|16|32] by imm8 -> r/m[8|16|32]

shift-left r/m[8|16|32] by %cl -> r/m[8|16|32]

shift-right r/m[8|16|32] by imm8 -> r/m[8|16|32]

shift-right r/m[8|16|32] by %cl -> r/m[8|16|32]

Description

sal (or its synonym shl) left shifts (multiplies) a byte, word, or long value for a count specified by an immediate value and stores the product in that byte, word, or long respectively. The second variation left shifts by a count value specified in the CL register. The high-order bit is shifted into the carry flag; the low-order bit is set to 0.

sar right shifts (signed divides) a byte, word, or long value for a count specified by an immediate value and stores the quotient in that byte, word, or long respectively. The second variation right shifts by a count value specified in the CL register. sar rounds toward negative infinity; the high-order bit remains unchanged.

shr right shifts (unsigned divides) a byte, word, or long value for a count specified by an immediate value and stores the quotient in that byte, word, or long respectively. The second variation divides by a count value specified in the CL register. shr sets the high-order bit to 0.

Example

Right shift, count specified by the constant (253), the 8-bit contents of the effective address (addressed by the ESI register plus an offset of 1):

sarb $253, 1(%esi)

Right shift, count specified by the contents of the CL register, the 16-bit contents of the effective address (addressed by the EDI register plus an offset of 4):

shrw %cl, 4(%edi)

Left shift, count specified by the constant (253), the 32-bit contents of the effective address (addressed by the EDI register plus an offset of 4):

shll $253, 4(%edi)