and{bwl} reg[8|16|32], r/m[8|16|32] and{bwl} r/m[8|16|32], reg[8|16|32] and{bwl} imm[8|16|32], r/m[8|16|32]
reg[8|16|32] land r/m[8|16|32] -> r/m[8|16|32]
r/m[8|16|32] land reg[8|16|32] -> reg[8|16|32]
imm[8|16|32] land r/m[8|16|32] -> r/m[8|16|32]
Performs a logical AND of each bit in the values specified by the two operands and stores the result in the second operand.
Table 2-2 Logical AND
Values |
Result |
---|---|
0 LAND 0 |
0 |
0 LAND 1 |
0 |
1 LAND 0 |
0 |
1 LAND 1 |
1 |
Perform an 8-bit logical AND of the CL register and the contents of the effective address (addressed by the ESI register plus an offset of 1):
andb %cl, 1(%esi)
Perform a 16-bit logical AND of the constant, 0xffee, and the contents of the effective address (addressed by the AX register):
andw $0xffee, %ax
Perform a 32-bit logical AND of the contents of the effective address (addressed by the EDI register plus an offset of 4) and the EDX register:
andl 4(%edi), %edx