Figures

FIGURE 1-1 Teja 4.0 Overview Diagram

FIGURE 7-1 Eclipse-Based ADE GUI

FIGURE 7-2 Teja Project Settings

FIGURE 7-3 PacketClassifier Hardware Architecture - Inner Hardware

FIGURE 7-4 PacketClassifier Hardware Architecture - Outer Hardware

FIGURE 7-5 PacketClassifier Software Architecture - OS View

FIGURE 7-6 PacketClassifier Software Architecture - Late-Binding View

FIGURE 7-7 PacketClassifier Mapping

FIGURE 10-1 IPv4 DiffServ Internal Data Path

FIGURE 10-2 IPSec Gateway Application Architecture

FIGURE 11-1 UltraSPARC T1 Architecture

FIGURE 11-2 UltraSPARC T2 Architecture

FIGURE 11-3 UltraSPARC T1 Forwarding Packet Rate Limited by I/O Throughput

FIGURE 11-4 Instructions per Packet Versus Frame Size

FIGURE 11-5 UltraSPARC T2 Forwarding Packet Rate

FIGURE 11-6 Example of Pipelining

FIGURE 11-7 Pipelining Effect on Throughput

FIGURE 11-8 Parallelizing Encryption Using Multiple Strands

FIGURE 11-9 RLP Application Setup

FIGURE 11-10 Results From Configuration 1

FIGURE 11-11 Results From Configuration 2

FIGURE B-1 Example for the ipfwd Application

FIGURE B-2 Memory Allocation Stack