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PCI:SBus Comparison

PCI-PCI Bridge Device Supported

For PCI-PCI bridge device support, refer to "PCI Developer's Frequently-Asked Questions" at http://shasta.corp.sun.com/Rte66/.

Table 1-7 Sun Host/PCI Bridge Characteristics
 Characteristics Bus A  Bus B
 Data Transfer Width 64-bit 64-bit
 Clock Frequency 33/66 MHz capable 33 MHz capable
 Burst Size 64 bytes 64 bytes
 Number of Read Buffers One 64-byte for DMA One 64-byte for DMA
 Number of Write Buffers Two 64-byte for DMA One 64-byte for PIO Two 64-byte for DM One 64-byte for PIO
 Dual Address Cycles Bypass DMA only Bypass DMA only
 Fast back-to-back device In target mode only In target mode only
 Byte Swapping Yes for DMA   Yes for DMA
 Interrupt Latency 6 Cycles inside the IDU  6 Cycles inside the IDU
 Cache Line Size 64 bytes 64 bytes
 Number of cache lines 16 16
 Disconnected on Cache Line Target mode (DMA) only Target mode (DMA) only
 Configuration Mechanism (per Section 3.7.4 of PCI 2.1 Specification) Configuration Mechanism #2 Configuration Mechanism #2
 Configuration Space 256 byte; starting at physical address 1FE.0101.0000 256 bytes; starting at physical address 1FE.0100.0000
 I/O Space 8K; at physical address 1FE.0200.0000 8K; at physical address 1FE.0201.0000
 Memory Space 2G; at physical address 1FF.0000.0000 2G; at physical address 1FF.8000.0000
 Configuration Cycles Master mode only Master mode only
 Special Cycle Master mode only Master mode only
 Arbitrary byte enables  Consistent DMA only Consistent DMA only
 Peer-to-peer DMA On a single segment On a single segment
 Interrupt Four interrupt lines shared among PCI devices Four interrupt lines shared among PCI devices
 IOMMU page size 8K and 64K.; only 8K page size is used in the STC. 8K and 64K.; only 8K page size is used in the STC.
 DVMA addressing space (set by pci nexus driver) 64 Mbyte in Solaris 2.5.1; may be changed in later release of Solaris 64 Mbyte in Solaris 2.5.1; may be changed in later Solaris releases
 PIO read size 1, 2, 4, 8, 16, 64 bytes for memory cycles1,2, and 4 bytes for I/O or configuration cycles 1, 2, 4, 8, 16, 64bytes for memory cycles1,2, and 4 bytes for I/O or configuration cycles
 PIO write size 0-16 arbitrary byte enable and 64-byte aligned for memory cycles0-4 arbitrary byte enables for I/O or configuration cycles  0-16 arbitrary byte enable and 64-byte aligned for memory cycles0-4 arbitrary byte enables for I/O or configuration cycles
 Cache-line wrap addressing mode Not supported Not supported
 Local (on-PCI) cache Not supported Not supported
 Exclusive access to main memory  LOCK# signal not connected LOCK# signal not connected
 Address/data stepping Not supported Not supported
 DOS compatibility hole Not supported Not supported
 External arbiter Not supported Not supported
 Subtractive decode Not supported Not supported