x86 Assembly Language Reference Manual

Miscellaneous Instructions

Write Back and Invalidate Cache (wbinvd) [486 only]

wbinvd
Example

Write back and invalidate the cache.

wbinvd

Invalidate (invd) [486 only]

invd
Example

Invalidate the entire cache.

invd

Invalidate Page (invlpg) [486 only]

invlpg	mem32
Example

Invalidate a single entry in the translation lookaside buffer.

invlpg 5(%ebx)

LOCK Prefix (lock)

lock
Operation

LOCK# -> NEXT Instruction

Description

The LOCK # signal is asserted during execution of the instruction following the lock prefix. This signal can be used in a multiprocessor system to ensure exclusive use of shared memory while LOCK # is asserted. The bts instruction is the read-modify-write sequence used to implement test-and-run.

The lock prefix works only with the instructions listed here. If a lock prefix is used with any other instructions, an undefined opcode trap is generated.

bt, bts, btr, btc

m, r/imm 

xchg

r, m 

xchg

m, r 

add, or, adc, sbb, and, sub, xor

m, r/imm 

not, neg, inc, dec

Memory field alignment does not affect the integrity of lock.

If a different 80386 processor is concurrently executing an instruction that has a characteristic listed here, locked access is not guaranteed. The previous instruction:

Example

lock

No Operation (nop)

nop
Operation

NO OPERATION

Description

No operations are performed by nop. The xchgl %eax, %eax instruction is an alias for the nop instruction.

Example
nop

Halt (hlt)

hlt
Address Prefix
addr16
Data Prefix
data16
Operation

HLT -> ENTER HALT STATE

Description

halt puts the 80386 in a HALT state by stopping instruction execution. Execution is resumed by an nmi or an enabled interrupt. After a halt, if an interrupt is used to continue execution, the saved CS:EIP or CS:IP value points to the next instruction (after the halt).

The halt instruction is privileged.

Example
hlt