This section describes the instructions that the assembler accepts. The detailed specification of how the particular instructions operate is not included; for this, see Intel's 80386 Programmer's Reference Manual.
The following list describes the three main aspects of the SunOS x86 assembler:
All register names use the percent sign (%) as a prefix to distinguish them from symbol names.
Instructions with two operands use the left one as the source and the right one as the destination. This follows the SunOS operating environment assembler convention, and is reversed from Intel's notation.
Most instructions that can operate on a byte, word, or long may have b, w, or l appended to them. When an opcode is specified with no type suffix, it usually defaults to long. In general, the SunOS assembler derives its type information from the opcode, where the Intel assembler can derive its type information from the operand types. Where the type information is derived motivates the b, w, and l suffixes used in the SunOS assembler. For example, in the instruction movw $1,%eax the w suffix indicates the operand is a word.
Three kinds of operands are generally available to the instructions: register, memory, and immediate. Indirect operands are available only to jump and call instructions.
The assembler always assumes it is generating code for a 32-bit segment. When 16-bit data is called for (e.g., movw %ax, %bx), the assembler automatically generates the 16-bit data prefix byte.
Byte, word, and long registers are available on the x86 processor. The instruction pointer (%eip) and flag register (%efl) are not available as explicit operands to the instructions. The code segment (%cs) may be used as a source operand but not as a destination operand.
The names of the byte, word, and long registers available as operands and a brief description of each follow. The segment registers are also listed.
Table 1-4 8-bit (byte) General Registers
%al |
Low byte of %ax register |
|
%ah |
High byte of %ax register |
|
%cl |
Low byte of %cx register |
|
%ch |
High byte of %cx register |
|
%dl |
Low byte of %dx register |
|
%dh |
High byte of %dx register |
|
%bl |
Low byte of %bx register |
|
%bh |
High byte of %bx register |
Table 1-5 16-bit (word) General Registers
%ax |
Low 16-bits of %eax register |
%cx |
Low 16-bits of %ecx register |
%dx |
Low 16-bits of %edx register |
%bx |
Low 16-bits of %ebx register |
%sp |
Low 16-bits of the stack pointer |
%bp |
Low 16-bits of the frame pointer |
%si |
Low 16-bits of the source index register |
%di |
Low 16-bits of the destination index register |
Table 1-6 32-bit (long) General Registers
%eax |
32-bit general register |
%ecx |
32-bit general register |
%edx |
32-bit general register |
%ebx |
32-bit general register |
%esp |
32-bit stack pointer |
%ebp |
32-bit frame pointer |
%esi |
32-bit source index register |
%edi |
32-bit destination index register |
Table 1-7 Description of Segment Registers
%cs |
Code segment register; all references to the instruction space use this register |
%ds |
Data segment register, the default segment register for most references to memory operands |
%ss |
Stack segment register, the default segment register for memory operands in the stack (i.e., default segment register for %bp, %sp, %esp, and %ebp) |
%es |
General-purpose segment register; some string instructions use this extra segment as their default segment |
%fs |
General-purpose segment register |
%gs |
General-purpose segment register |