Here is a mapping of synthetic instructions to hardware equivalent instructions.
Table E-12
Synthetic Instruction |
Hardware Equivalent(s) |
Comment |
||
---|---|---|---|---|
cas casl casx casxl |
[regrsl], regrs2, regrd [regrsl], regrs2, regrd [regrsl], regrs2, regrd [regrsl], regrs2, regrd |
casa casa casxa casxa |
[regrsl]ASI_P, regrs2, regrd [regrsl]ASI_P_L, regrs2, regrd [regrsl]ASI_P, regrs2, regrd [regrsl]ASI_P_L, regrs2, regrd |
Compare & swap (cas) cas little-endian cas extended cas little-endian, extended |
clrx |
[address] |
stx |
%g0, [address] |
Clear extended word |
clruw clruw |
regrs1, regrd regrd |
srl srl |
regrs1, %g0, regrd regrd, %g0, regrd |
Copy and clear upper word Clear upper word |
iprefetch |
label |
bn, pt |
%xcc, label |
Instruction prefetch, |
mov mov mov |
%y, regrd %asrn, regrd reg_or_imm, %asrn |
rd rd wr |
%y, regrd %asrn, regrd %g0, reg_or_imm, %asrn |
|
ret retl |
|
jmpl jmpl |
%i7+8, %g0 %o7+8, %g0 |
Return from subroutine Return from leaf subroutine |
setn |
value, r1, r2 |
for -xarch=v9 same as setx value r1, r2 for -xarch=v8 same as set value r2 |
|
|
setnhi |
value, r1, r2 |
for -xarch=v9 same as setxhi value r1, r2 for -xarch=v8 same as sethi value r2 |
|
|
setuw |
value,regrd |
sethi or sethi or |
%hi(value), regrd %g0, value, regrd %hi(value), regrd; regrd, %lo(value), regrd |
(value & 3FF16)==0 when 0 <= value <= 4095 (otherwise) Do not use setuw in a DCTI delay slot. |
setsw |
value,regrd |
sethi or sethi sra sethi or sethi or sra |
%hi(value), regrd %g0, value, regrd %hi(value), regrd regrd, %g0, regrd %hi(value), regrd; regrd, %lo(value), regrd %hi(value), regrd; regrd, %lo(value), regrd regrd, %g0, regrd |
value>=0 and (value & 3FF16)==0 -4096 <= value <= 4095 if (value<0) and ((value & 3FF)==0) (otherwise, if value>=0) (otherwise, if value<0) Do not use setsw in a CTI delay slot. |
setx |
value, r1, r2 |
sethi or sethi or sllx or |
%hh(value), r1 r1, %hm(value), r1 %lm(value), r2 r2, %lo(value), r2 r1, 32, r1 r1, r2, r2 |
|
setxhi |
value r1, r2 |
sethi or sethi sllx or |
%hh(value), r1 r1, %hm(value), r1 %lm(value), r2 r1, 32, r1 r1, r2, r2 |
|
signx signx |
regrsl, regrd regrd |
sra sra |
regrsl, %g0, regrd regrd, %g0, regrd |
Sign-extend 32-bit value to 64 bits |