Define cache properties for the optimizer.
SPARC: 77/90
c must be one of the following:
generic
s1/l1/a1
s1/l1/a1:s2/l2/a2
s1/l1/a1:s2/l2/a2:s3/l3/a3
The si/li/ai are defined as follows:
si The size of the data cache at level i, in kilobytes
li The line size of the data cache at level i, in bytes
ai The associativity of the data cache at level i
This option specifies the cache properties that the optimizer can use. It does not guarantee that any particular cache property is used.
Although this option can be used alone, it is part of the expansion of the -xtarget option; it is provided to allow overriding an -xcache value implied by a specific -xtarget option.
Table 3-20 -xcache Values
Value |
Meaning |
---|---|
generic |
Define the cache properties for good performance on most SPARC processors without any major performance degradation. This is the default. |
s1/l1/a1 |
Define level 1 cache properties. |
s1/l1/a1:s2/l2/a2 |
Define levels 1 and 2 cache properties. |
s1/l1/a1:s2/l2/a2:s3/l3/a3 |
Define levels 1, 2, and 3 cache properties |
Example: -xcache=16/32/4:1024/32/1 specifies the following:
A Level 1 cache has: 16K bytes, 32 byte line size, 4-way associativity.
A Level 2 cache has: 1024K bytes, 32 byte line size, direct mapping associativity.