postrc(4)

NAME | CAUTION | DESCRIPTION | PROPERTIES | SEE ALSO

NAME

postrc- (.postrc) hpost properties file

CAUTION

Many of the .postrc directives are appropriate only in an engineering or manufacturing environment. Others might be appropriate for field use, but only by a qualified service provider or properly trained system administrator. Users without specific training in the use of these features should not use them.

DESCRIPTION

The .postrc file is an ASCII text file that contains the various configurable properties of the hpost(1M) program; it controls options in POST.

Some hpost(1M) functions can also be controlled from the command line. Such functions are clearly marked in the descriptions that follow. Command line arguments take precedence over commands in the .postrc file, which take precedence over built-in defaults. For a terse reminder of the .postrc options and syntax, enter hpost -?postrc.

Unless -n is the first argument on the hpost line, hpost reads the optional file .postrc, and executes the directives in that file before it begins operation with the host. If hpost does not find .postrc it proceeds without it. hpost first looks for .postrc in the current directory (.). If it does not find it there, hpost looks in $SSPVAR/etc/platform_name/$SUNW_HOSTNAME. If it does not find .postrc there, it looks in the user's home directory, $HOME. Exception: If the current directory is $HOME, the first element of the search path (.) is skipped. This exception allows a domain-specific .postrc file to take precedence over the user's default $HOME/.postrc when running from the user's home directory, while still allowing use of a local ./.postrc to take precedence as long as the user is currently in any directory other than the user's home directory.

Some of the commands described below are accepted only when the local file ./.postrc is used; such commands are clearly marked. These commands are never available when the current directory is $HOME, as the ./.postrc search path is skipped in such cases.

The following rules apply to the .postrc file:

• Keywords are case-sensitive.

• Numeric arguments are decimal by default, taken as hex if preceded by 0x or x.

• Keywords and optional arguments are delimited by whitespace.

• Any part of a line that begins with a pound sign (#) is considered a comment and ignored.

PROPERTIES

The following list of properties is provided in alphabetical order. Each of these commands can also be classified by the appropriate user level, as designated by the number in parentheses at the end of the title line. The levels are:

Level 1

System Administrator Commands. These commands control functionality either intended for system administrator control or safe because their effect is essentially benign (for example, logfile).

Level 2

Commands for use by Sun Microsystems and service providers only.

Level 3

Commands for use by Sun Microsystems POST developers (for debug) and Sun Microsystems engineers only.

allow_lab-only_components (Level 3)

SMI engineering labs sometimes need to operate systems containing hardware that is not acceptable for customer machines. These components are often early prototype parts with known bugs or speed problems, for example. Such parts cannot inadvertently find their way into a production system. POST normally rejects and fails these parts immediately, based on their Component ID (CID) values. To support the engineering lab requirement, the allow_lab-only_components command instructs POST not to perform this CID-based rejection, and to accept certain specific values that are recognized but identified as lab-only. This command does not disable all CID checks, it just expands the list of acceptable CIDs.

allow_sys_errctl (Level 3)

When JTAG-configuring the PC, CIC, or MC ASICs, always enable system register write/clear access to error status, error mask, and force error registers. This property is normally enabled only when diagnostic code (such as POST) is run, and not in the final configuration.

alt_level level (Level 1)

Use level as the POST level, rather than the default alternate level, if the -a command argument is invoked. However, if the level command is also invoked, and specifies a higher value, that higher value is used.

This -a mechanism is intended for certain error reboot scenarios, to run higher-than-normal levels of diagnostics. However, regardless of the level specified by alt_level, -a will not result in hpost running at a lower level than if -a were not invoked.

arb_flip_ctr_limit value (Level 3)

All of the Sun Enterprise 10000 arbitration ASICs reverse the priority order of their clients' requests after some number of grants to improve the fairness of the arbitration algorithm. The number of grants is programmable when the ASIC is configured. A default value is normally used. This command allows Sun Microsystems engineering to experiment with this value.

asic_ignore asic_type (Level 3)

Do not test, configure or dump the named ASIC type. This command allows Sun Microsystems engineering to exercise POST code in development systems in which certain ASICs do not exist, which would otherwise cause POST to fail immediately. To get a list of the available asic_type keywords, use hpost -?postrc.

assume_ldarb_rev_2 (Level 3)

Do not check the CID of LDARB ASICs to understand how to set their configuration; just assume they are not rev 1. This command supports a special mode of POST (see scantool_simulate) used to provide the JTAG configuration as input to Verilog ASIC simulation, in which no ASIC input is possible.

blacklist_file {file | none} (Level 2)

Command Line Equivalent: -X Use the specified blacklist(4) file rather than the default, $SSPVAR/etc/platform_name/blacklist. file can be the path to the blacklist(4) file or none. If it is none, POST reads no blacklist file.

Be careful when using blacklist_file on a production system; other SSP software does not know when POST is using a nonstandard blacklist(4) file.

board_red_any_fail (Level 2)

If any failure is detected on a board, immediately fail and effectively redlist all the resources on the board. This line is intended to prevent further configuration of the board, so that a postmortem analysis of the stop can be performed. See also system_red_any_fail and redlist(4).

bus_shuffle_mode {0|1|2} (Level 3)

A facility in the PC ASIC allows the assignment of addresses to GABs to be varied from the default, which has it based on PA[8:6], with the exact assignment depending on how many and which GABs are configured. This default is shuffle mode 0. Shuffle mode 1 uses PA[8:6] XOR PA[18:16], shuffle mode 2 uses PA[8:6] XOR PA[20:18]. This command allows Sun Microsystems engineering to experiment with the effect of this shuffle capability.

cplane_initial_config (Level 3)

Command Line Equivalent: -C Start POST in the initial (rather than a subsequent) domain. Several independent domains can be running on an Sun Enterprise 10000 system, but unless they are in isolated_sysboard mode, they all share the centerplane ASICs, which can be in only one functional bus configuration. By default, POST assumes it is not running in the first domain being brought up. So it probes the centerplane to determine the bus configuration, and constrains itself to use that configuration. Also, it does not do the functional configuration of the centerplane ASICs.

The usual way to start POST running in the initial domain is through the -C command line option. When POST is running in the initial domain, it must establish the bus configuration and do the initial centerplane ASIC configuration.

This command (and the -C command line option) starts POST in the initial domain, where it must establish the bus configuration and do the initial centerplane ASIC configuration.

cplane_initial_config is equivalent to the -C command line option for the convenience of Sun Microsystems engineering, manufacturing and customer service technicians who must repeatedly run POST on uninitialized systems.

Do not use this command on production systems that run, or might someday run, multiple domains, as it can cause POST running in the domain brought up second to crash anything running in the domain brought up first.

debug_mask mask (Level 2/3)

Use mask as the debug mask. This is a bitmask that controls experimental code or obscure behavior modes of POST. It is mostly for POST developer use. The mask is ORed into the internal mask, allowing one line/bit, so bits can be added/removed by the commenting out of a list in the .postrc file. Because these bits change over time, users should execute hpost -?postrc for a list of current bits.

default_ecache_mbytes {H|1|2|4|8|16|32} (Level 2)

Assume the specified Ecache size for all processors if the Ecache probe, done as part of the initial processor test phase, is skipped. If the probe is skipped and this value is incorrect, the configured system will not maintain correct cache coherency. The "default default" is 0.5 Mbyte - "H".

default_memgrp_mbytes {64|256|1024} (Level 2)

Use the specified DIMM group size as the default. The default size is used for Figure of Merit (FOM) calculations prior to the DIMM probe phase, and also as the assumed value of all good DIMM groups if the DIMM probe phase is skipped by the skip_phase command. The "default default" is 64 Mbyte.

display_fom_calc {off|on} (Level 1)

If on, always make POST print the calculated FOM for all 45 bus configurations when it is making an FOM calculation to select a configuration. If off, never do so. If this command is not present, POST does the printing if the verbose level is above a certain value.

dom_transgress_err_enbl (Level 2)

Enable reporting of Domain Transgression Errors by the GDARB ASIC when configuring the centerplane, which is done when hpost is called with the -C option. (See cplane_initial_config). A transgression error occurs when a system board's data arbiter requests to send data to a board in a different domain cluster as defined by the GDARB's SMD mask configuration register.

By default, reporting of these errors is disabled to minimize the probability of GDARB asserting a global arbstop when a board fails and causes both a parity error and a transgression error. GDARB does inhibit transgressing requests; it just does not report them as errors. This dom_transgress_err_enbl command enables this error reporting, for cases where the additional fault detection is preferred over the additional domain fault isolation.

domain boardmask (Level 3)

Declare a set of system boards to be a domain. Domains are disjoint partitions of the system boards in an Sun Enterprise 10000 system that are isolated from each other, except for shared memory (see command shared_mem).

This .postrc command is not how domains are managed in production systems; it is a static instruction to POST to configure the domain registers for Sun Microsystems engineering debug of the domain hardware. This domain command is effective only when used in a .postrc file in the current directory. If the .postrc file used is not in the local directory, POST ignores this command and generates a warning message.

download_bbsram_verify {off|on} (Level 2)

If on, always verify that each JTAG POST code download to a processor BBSRAM actually occurred. If off, never do so. If it is not specified, verification is done only if the level is above a certain value. To do the verification, download_bbsram_verify uploads code from BBSRAM and compares it to the code file data. Unlike download, which is done with a JTAG broadcast, the upload and compare must be done serially for each processor.

download_path dirpath (Level 2)

Use the download files for POST that are in the location dirpath. The default is $SSPOPT/release/Ultra-Enterprise-10000/*/*/*/hostobjs, where /*/*/*/ indicates a release-level dependency.

dtag_test_all_procs (Level 2)

Normally, POST assigns each processor to test its own DTAG RAM for each CIC on the board. This process ensures that only resources that can be used are tested, as DTAG RAM for missing or failed processors is not usable for anything else. However, in some environments, such as manufacturing test, Sun Microsystems prefers that all the DTAG RAM be tested, in preparation for future installation of additional processors. This command causes each processor, during the DTAG RAM test phase, to test all the RAM on each CIC, not just its own. For the same reasons, this command also causes testing of all physically present DTAG SRAM locations, not just those that will be used to support the size of Ecache on the currently installed processor modules.

dump_no_sneeprom (Level 3)

When creating a dump file, either with the -D command line option or automatically when certain errors are encountered while POST is running, do not include the contents of the serial number EEPROMs in the dump. This command can significantly speed up the dump process in some environments. It can be removed in the future.

dump_on_exit [boardmask [path]] (Level 2)

Make POST create a dump file of the system state just before it exits. The boardmask controls what boards are dumped, where bits [15:0] control system boards and [17:16] control half-centerplanes. The board is dumped if the corresponding bit is 1. The default is x3FFFF (dump all). This would normally be specified as a hex value. path can be used to override the default path for the dumpfile. A path can be specified only if a boardmask is specified. Both options are similar to those of the -D command line option.

dump_pathname dirpath (Level 2)

Create state dump files in the specified default directory rather than the program default, $SSPVAR/adm/$SUNW_HOSTNAME. If a path has been specified by either the command line option (-D) or the dump_on_exit command, that path overrides the one specified by dump_pathname.

fom_weight_abus float-in_range (Level 1)

Use the specified weight of the number of address buses in the FOM computation. The float-in range is 1.0 to 5.0; the default is 1.0.

fom_weight_dbus float-in_range (Level 1)

Use the specified weight of the number of data buses (72-bit datapaths) in the FOM computation. The float-in range is 1.0 to 5.0, inclusive; the default is 1.0.

fom_weight_mem float-in_range (Level 1)

Use the specified weight of memory in the FOM computation. The float-in range is 1.0 to 5.0, inclusive; the default is 1.0.

fom_weight_proc float-in_range (Level 1)

Use the specified weight of processors in the FOM computation. The float-in range is 1.0 to 5.0, inclusive; the default is 1.0.

fom_weight_scard float-in_range (Level 1)

Use the specified weight of SBus cards in the FOM computation. The float-in range is 1.0 to 5.0, inclusive; the default is 1.0.

force_dtag_parity_mode (Level 2)

If a Sun Enterprise 10000 system board is populated with Revision 2 CIC ASICs, POST normally configures those CICs for Dtag Error Checking and Correction (ECC) mode, provided that the on-board processors have the minimum external cache (Ecache) size required to support Dtag ECC mode. ECC allows single-bit errors in Dtag SRAM reads to be corrected by the CIC hardware without affecting domain operation. However, single-bit errors in parity mode cause fatal arbstop errors. This property tells POST to always configure CICs in Dtag parity mode, even when ECC mode is possible.

force_enbl_cp_driver (Level 3)

Sun Enterprise 10000 system ASICs that connect to the centerplane have both a loopback control and a separately controlled enable for the centerplane drivers. Normally, POST configures these ASICs so that the drivers are disabled when the chip is in loopback, and enabled when it is not. For probing the board signals, it is sometimes useful to drive the centerplane connector with the address and data buses even when in loopback. This command causes all ASICs to have their centerplane drivers enabled, even when configured in board loopback. See also pc_loopback_lbus_enbl.

gamux_seq_err_enbl (Level 2)

Early GAARB revisions, which should never be shipped in production machines, have a design bug that causes sequence errors that will be detected by the GAMUX ASICs when an arbstop occurs for some other reason in one domain. Since these sequence errors are considered global errors, this bug results in an arbstop in all other domains, as well.

By default, detection of these sequence errors is disabled when the GAARBs are rev 1 or 2, and enabled otherwise. The gamux_seq_err_enbl command allows explicit control, disabling detection of these errors when set to 0, enabling it when set to 1 - regardless of GAARB revision.

interactive_use_postrc_skips (Level 2)

When running in interactive mode (-i command line option), the default behavior is to ignore any skip_phase or skip_test commands in the .postrc file, giving the user the option of running or skipping each interactively. In some cases, that might not be the desired behavior; the user might not want to have to interactively skip dozens of phases and tests to get to the one of interest. This command causes POST to use any skip_phase or skip_test commands, and not query the user about whether to run them. See also the no_skip_phase_covers_npb command; the implied skips described there are considered to be in the .postrc file with respect to this command.

interconnect_MHz float (Level 2)

Use the specified system interconnect frequency, expressed in megahertz. This value is used for calculating system configuration parameters (most particularly, memory timing) in teststand environments lacking a real control board that can measure and report this frequency through the SNMP server.

In systems that do have a control board, where use of the SNMP frequency measurement is used, specifying this value causes POST to require that the measured value be within 0.5 percent of this value. If it is not specified, the measured value must be within -3.0 and +0.5 percent of the target interconnect frequency read from the SNMP server.

See also proc_freq_ratio.

iopc_rev_5_ok (Level 2)

The rev-5 PC ASIC has a bug that occurs when the ASIC is used in the I/O position, PC number 2 on any system board. The effects of the bug might be acceptable for certain applications, with or without certain software workarounds installed. POST normally fails these ASICs, but accepts them if their presence is explicitly acknowledged with this command.

jtag_lock_trace (Level 2)

Make POST print verbose debugging messages about its actions with respect to the locking and unlocking of JTAG boards and rings.

isolated_sysboard (Level 2)

Make POST ignore the fact that the centerplane ASICs appear missing or broken, which would normally cause it to fail immediately; and prevent POST from taking the board out of loopback. This function is used in development environments that do not have a centerplane.

jtag_lock_timeout_secs value (Level 2)

Change the default timeout value for obtaining a lock on a JTAG resource from the SSP core services.

level level (Level 1)

Command Line Equivalent: -l Use the specified level to determine the amount of testing to be done and the thoroughness with which it is done. Higher levels result in more testing. Valid levels are in the range 7 to 127, inclusive. hpost -?level prints a brief summary.

This command is suitable for end user control, but do not set the level lower than normal. Doing so subverts the intent to boot only systems with a low likelihood of undetected hardware problems. Setting it higher than the default (see the -l option of hpost(1M)) might be appropriate for customers willing to trade longer boot times for more thorough diagnostic coverage.

logfile [path] (Level 1)

Command Line Equivalent: -g Create a screen logfile. The default filename is postmmdd.hhmm.log and the default directory is $SSPVAR/adm/$SUNW_HOSTNAME/post. If the default path is used and the default directory does not exist, but $SSPVAR/adm/$SUNW_HOSTNAME does, POST creates the post subdirectory and places the log there.

If path is specified and it can be opened for append, POST creates the log there. Otherwise, if the default file name can be opened in path used as a directory, POST creates the log there. If a log is requested and none of the above is specified or successful, POST attempts to create the logfile in the current directory with the default name.

The logfile is always opened for append, and is timestamped both when opened and closed, so that a calling script or program can specify a single file to receive logs from a series of POST runs, and to prevent loss of information in the unlikely event of a name conflict.

This command is rated Level 1 because it is fairly benign, other than using up SSP disk space. However, note that in a production environment, POST output is usually diverted (by the bringup(1M) script using -s) to syslog, which can be a more appropriate way to save this information in production environments.

logger_level{default|emerg|alert|crit|err|warn|notice|
info|debug} (Level 2)

POST captures all liblogger messages produced by the libraries it uses, so they can be part of its own displays and logs. Normally, it also overrides the default logger level to WARNING, so that the contents of its displays are not subject to external control. This command causes POST to either not override the current default logger level it inherits from the environment, allowing it to be controlled by the normal logger mechanisms, or to explicitly set the logger level to any desired value.

If the .postrc file used is not in the local directory, POST ignores this command and generates a warning message.

logical_memboard_swap slot1 slot2 (Level 3)

Exchange the logical memory board numbers of the two named physical system boards. Physical memory addresses are assigned by POST starting at 8 Gbyte * logical board number. By default, the assignment of a logical memory board to a physical system board is 1-1. Swaps can occur over time, for example, as the result of dynamic reconfiguration board detach operations, or the sort done by POST as explained in the description of the command no_memboard_sort. In a production system SSP, this physical-to-logical mapping is kept in the SNMP MIB and read by POST each time it runs. This command allows Sun Microsystems engineering to use non-default mappings in lab environments where SNMP is not running.

Any number of these commands can be present; the swaps occur in the order requested. The only constraints are that the two arguments are different valid system board numbers.

This command is effective only when used in a .postrc file in the current directory. If the .postrc file used is not in the local directory, this command is ignored and a warning message is generated.

Any swapping caused by this command is overwritten by the map information obtained from SNMP, and effectively ignored, unless that access is inhibited with the command no_snmp_memmap or no_snmp_access. Such swaps cannot be done in combination with the map obtained from SNMP; the two are mutually exclusive.

mc_gabfifo_hold_depth 6-bit value (Level 3)

Override normal MC ASIC configuration of this field, which is the constants register bits [17:12].

mc_prescale_disbl (Level 2)

Override normal MC ASIC configuration which causes all timeouts to be prescaled by 2**10 system clocks. This field is the Timeout Select register bit 23.

mc_store_match_to 5-bit_value (Level 2)

Override normal MC ASIC configuration of this field. This field is the Timeout Select register bits [9:5].

mc_timing_reg reg value (Level 3)

Override normal MC ASIC configuration of the specified memory timing control register [3:0], where register 0 is refresh timing, register 1 and 2 are memory timing 1 and 2, and register 3 is DIMM wire timing.

mc_xmit_req_to 5-bit_value (Level 2)

Override normal MC ASIC configuration of this field, which is the Timeout Select register bits [4:0].

mc_xtra_data_to 5-bit_value (Level 2)

Override normal MC ASIC configuration of this field, which is the Timeout Select register bits [14:10].

mem_board_interleave_ok (Level 1)

Permit POST to configure memory so that two boards with identical amounts of memory are interleaved in 256-byte blocks through a common address range, which is twice what either board would otherwise contain.

Interleaving can improve performance by distributing memory accesses of large blocks of contiguous data between two memory controllers. However, interleaving two boards can have the effect of restricting dynamic reconfiguration (DR); in particular, it can prevent an interleaved board from being DR detached.

The default POST behavior is to not interleave boards. This command enables interleaving of any two boards with the same amount of memory.

memboard_sort_order {low_to_high | high_to_low} (Level 2)

Specify the preferred ordering of assignments of memory physical addresses to system boards within this domain. low_to_high places low addresses on low-numbered system boards and high addresses on high-numbered system boards. high_to_low places addresses on system boards in the opposite order.

If this memboard_sort_order command is not present, the order is determined by examination of the version of the Solaris operating environment specified in the SSP's SNMP MIB for this domain. If the version is earlier than Solaris 7, it uses low_to_high. However, the Solaris 7 operating environment is the first to use high_to_low. If access to the SNMP MIB is also suppressed with the command no_snmp_access, the default is low_to_high.

The purpose of this ordering is to place kernel memory on the lowest-numbered boards, to allow complex systems to be optimally configured for DR without regard to operating system version.

See also the commands no_memboard_sort and no_memboard_fullsort.

memboard_swap_threshold_mbytes mbytes (Level 2)

This command defines the minimum amount of memory that must be on the lowest-numbered physical board with memory in the domain, to avoid swapping its physical addresses with those of the board in the domain with the most memory. See the command no_memboard_sort for an explanation of the sort and how it can be disabled.

The objective of this swap is to have enough memory in the physical address chunk used for kernel memory in the domain for the DR "caged kernel" to fit within this single board, increasing the likelihood that any board can be DR detached. However, if the first board has a required minimum amount of memory, the swap is not required even if another board has yet more memory, and Sun Microsystems engineering desires to avoid this unnecessary swap.

The default and minimum value of this no-swap threshold is 512 Mbyte. This command is provided to allow field increases of this threshold if the caged kernel characteristics change. The maximum is 4096 (4 Gbyte), which is all the memory a board can contain with the largest supported memory DIMMs.

memchunk_page_truncate #_of_8KB_pages_per_chunk (Level 3)

Limit the amount of memory declared in the memory chunk list passed to OBP and cleared in the final configuration phase. If the number of pages in a contiguous chunk (usually the physical memory of one board or a pair of interleaved boards) is greater than this value, truncate it to the declared size. This command does not affect the configuration of the memory controller, only how much memory is declared to OBP and cleared. It is intended for controlled debug environments that can deal with a portion of configured physical memory not initialized, to save time, and is most useful in an emulation environment.

memtest_limit [base] limit (Level 2)

Limit the amount of memory tested in each DIMM group by the POST memory tests. If only one argument is supplied, it is used as the limit and the base is left at 0.

Both values represent byte offsets within each group, as if it were configured at PA 0 without any interleaving. In general, this does not correspond to the physical addresses a given group is assigned in a fully configured machine, or those used during the memory tests themselves. In particular, memory testing is always done as if the banks were four-way interleaved, even if not all four banks are present. Each processor tests a range of addresses four times the number of bytes it is testing, but it tests only 64 bytes out of each 256 within that range, all of which are in the same DIMM group.

These limits are applied to every group tested. Since memory is tested only in 64-byte blocks, both arguments must be mod-64. The maximum for both is 0x40000000, or 1 Gbyte, which is the full size of a group of the largest DIMMs supported. The limit must be greater than the base. If the base is greater than a physical group's size, that group is (quietly) not tested.

new_cid_rev component_id (Level 2)

During its JTAG integrity test phase POST reads the component IDs of all the ASICs, as well as other chips that have a CID, and compares them against tables of acceptable CIDs for these chips. In general, discrepancies result in POST failing the chip. However, if a CID matches a value in the table except for the revision (the most significant hex digit of an 8-digit CID), and the actual revision is higher than the revision in the table, the chip is accepted and POST issues a warning about the up-level chip.

This process adds resilience to hardware upgrades without forcing distribution of a POST patch. It also serves notice that POST might not be aware of all features and requirements of all present hardware, so that if any hardware problems occur, the chip-version issue will be immediately obvious.

While the up-level message is only a warning, it might make some users uncomfortable. The purpose of this new_cid_rev command is to effectively add an entry to the CID table to suppress the up-level warning. The .postrc file can contain multiple instances of this command. POST consults the list of values they create only when it is about to issue an up-level warning message. Thus, you cannot use new_cid_rev commands to declare new base CIDs, or to declare that a down-level CID revision is acceptable. Since the base part of the entered CID must match that of at least one of the base CIDs in the compiled table for some chip for this command to have any effect, it is not necessary to specify in this new_cid_rev command which chip type is having its table extended.

Service providers should use this facility to suppress the up-level warnings only when notified by Sun Microsystems engineering that a specific up-level chip is really equivalent to the older revision compiled into POST.

Normally, component_id would be entered as an 8-digit (32-bit) hex value. It is checked only to be sure that it satisfies the requirement of any valid CID; that is, to ensure that its least significant digit is 1.

no_asic_config_check (Level 3)

Skip the normal readback and compare of ASIC CSRs written by JTAG when configuring the system. This command is useful in certain development environments during system simulation.

no_bbc_error_check (Level 2)

POST usually checks the BootBus error status register in the PC, at the end of major phases, for BootBus parity or access errors. Errors usually result in POST failing the PC. This command suppresses all checks of this register.

no_bbsram_clear (Level 2)

POST normally writes all of BBSRAM to prevent parity errors if some code accesses an uninitialized address. It does so on the first code download of a file declared to need a signature block, to avoid interfering with the special BootBus SRAM test file. To save download time, POST fills only those segments of BBSRAM that not loaded with code or data, and it does so only once.

This command suppresses this fill, so that areas of BBSRAM not explicitly loaded by the code are left untouched.

no_check_chain_length (Level 2)

During its JTAG integrity test phase, POST checks that all chips with component IDs have one that is the standard 32-bits long. This simple but useful test ensures that the chip's JTAG scan connection is reliable. This command makes POST skip the chain length test, but still do the probing operations of the JTAG integrity test phase.

no_dtag_ecc_ce_scrub (Level 2)

Revision 2 CIC ASICs configured in Dtag ECC mode will correct any single-bit errors that are detected during Dtag SRAM accesses. Normally, the corrected data is also written back to the SRAM. This function, which is called scrubbing, fixes the correctable errors (CE) of the Dtag SRAM and eliminates recurring CEs during subsequent Dtag SRAM accesses. This property tells POST to disable the scrubbing function in the CIC ASIC configuration.

no_dumpfile_on_stop (Level 2)

Make POST suppress its normal action of creating a dumpfile of "interesting" system state if and when it detects an arbstop or recordstop during testing.

If this command is not present, POST dumps the system state, edits it to skip boards that have no interesting state, then analyzes the dump. If POST finds no boards with interesting state, it does not create a dumpfile and just moves on. (For example, data ecc error recordstops that originate in memory might cause POST to simply move on without creating a dumpfile.) See also dump_pathname.

If no_dumpfile_on_stop is not in .postrc but no_stop_analyze is, POST simply creates the dumpfile then moves on, neither editing nor analyzing it.

no_final_flush_reset (Level 2)

The normal action of POST is to pause and flush all nonredlisted processors' master queues in the PC ASIC, then reset each processor at the end of its final configuration. This leaves a state that facilitates download of OBP code to BBSRAM without any problems executing stale fetches from the POST spin-wait loop. If no_final_flush_reset is invoked, the processors are instead left spin-waiting in the POST final configuration code in BBSRAM, which can be useful for postmortems of final configuration processor state.

no_jtag_locks (Level 3)

SSP software that uses the JTAG communication facilities provided by the Sun Enterprise 10000 control board is normally expected to lock the JTAG ring or rings with which it is currently communicating to prevent multiple SSP applications (for example, POST and obp_helper(1M)) from interfering with each other. The locking is done through semaphore-based services provided by the SSP libraries.

This command causes POST to skip use of these locking services, which is useful in certain engineering development environments.

no_lockfile (Level 3)

Permit multiple POST processes to run simultaneously on the same Sun Enterprise 10000 host domain. POST normally creates the lockfile $SSPVAR/adm/$SUNW_HOSTNAME/hpost.lock to prevent multiple instances of POST, since mutual interference is likely to occur, causing both POST processes to fail.

In a normal SSP environment, POST is usually run in daemon mode. It is not always obvious that this is happening and, in a development environment, it often interferes with user-initiated POST processes.

However, occasionally allowing two POST processes to run is considered less of a problem than POST refusing to run due to a stale lockfile. Therefore, if creation of the lockfile fails, POST attempts to validate that it was created by another active POST process. If this attempt fails, POST enters -f mode (described below) and proceeds to run, deleting any lockfile when it exits. This process provides automatic recovery from most cases in which a lockfile is left from an abnormally terminated POST process.

The effect of this no_lockfile command is to completely disable the lockfile function, both file creation and removal.

Note that this is significantly different from the -f command line argument. With -f, POST still tries to create a lockfile, but continues even if that fails; and it attempts to delete the lockfile at exit, even if the create failed. The purpose of -f is recovery from a stale lockfile that incorrectly appears to belong to an active POST process.

no_mc_hardreset (Level 2)

The memory controller (MC) ASIC has some functions, most notably memory refresh, that are not affected by normal system reset. These functions are cleared only by a hard reset, which can be caused by the JTAG TAP reset pin, and which occurs during a power-on reset, or by a special hard reset control bit in a JTAG config register. It is possible, particularly when LBIST is run, to leave the MC in a state that requires a hard reset to make it usable.

POST normally asserts a hard reset to all MC ASICs during the initial reset phase. This command causes the hard reset to be skipped, which might be useful in some test environments. This hard reset is also skipped if POST is run in the special -Z reconfiguration mode.

no_memboard_fullsort (Level 2)

Suppress the full sorting of memory physical addresses to physical system boards. If this no_memboard_fullsort command is invoked, the assignment of physical addresses to system boards is taken from the SSP SNMP ConfMemMap MIB element without modification, except for the possible swap described for the command no_memboard_sort.

If this no_memboard_fullsort command is not invoked, a full sort of addresses within this domain is made in the order described under the description of the command memboard_sort_order. This sorted order is then subject to the possible swap described for the command no_memboard_sort.

no_memboard_sort (Level 2)

The default action of POST when running in a domain of two or more boards is to do a partial sort of the boards based on the amount of memory on each board. The object of this sort is to configure the domain such that the physical memory addresses used for kernel memory in the domain are on a board with the largest amount of memory, unless the amount on the lowest board is above a threshold amount. This optimizes the capabilities of some features of dynamic reconfiguration, as explained in the description of the command memboard_swap_threshold_mbytes.

Doing this sort might require a single physical-to-logical mapping swap of a board that would contain kernel memory in the domain with another board in the domain that has more memory. See the command logical_memboard_swap for more information about this mapping. Since the physical-to-logical mapping is maintained by the SNMP agent on the SSP, if a swap is required, POST must do a write operation to SNMP to inform it of the swap.

This command, no_memboard_sort, suppresses both the sorting and the SNMP write access. This suppression is implied if no_snmp_memmap or no_snmp_access is invoked. See also no_memboard_fullsort.

no_memory_ok (Level 2)

Since the operating system cannot boot without memory, the amount of memory is one component of the configuration Figure of Merit (FOM) used to evaluate configurations. No memory results in a zero FOM. For board bringup, however, Sun Microsystems sometimes wants POST to continue testing even with no memory installed. This command tells POST to pretend there is one unit (currently 64 Mbyte) of memory when calculating the FOM if there is actually none.

Other features in the processor modules and I/O require valid memory to be tested. Therefore, do not run board tests without memory as standard practice, as these other elements would not be tested. However, this capability is useful upon occasion.

no_non_proc_boards (Level 1)

Do not allow system boards without a processor on board. By default, nonprocessor boards (NPBs) are permitted, so that their onboard memory and I/O are not lost because of processor failures. In general, such configurations are fully functional.

In certain situations such NPBs might be undesirable. This command causes POST to remove such boards from the configuration, even though they might have usable I/O and/or memory.

no_obp_handoff (Level 2)

During the final configuration phase do not create the post2obp structures in BootBus SRAM of the boot processor. This command causes an otherwise successful run of POST to exit with POST_EXIT_NOCONFIG instead of a boot processor number (0 to 63, inclusive).

no_poll_board_arbstop (Level 3)

Suppress POST's normal polling for arbstop and recordstop. POST does the polling by reading the local address arbiter (LAARB) error register through JTAG. When this command is used, stops are detected in other ways, most often by timeouts. The processors, instead of the true cause of the error, are failed, and recovery capability is limited.

no_poll_timeouts (Level 3)

Disable all timeouts on the host processor RPC services. This is useful when running with breakpoints installed in the resident code of a host processor during Sun Microsystems engineering's debug of POST. Compare to poll_timeout_mult.

no_procs_ok (Level 2)

Since the operating system cannot boot without processors, the number of processors is one component of the configuration Figure of Merit (FOM) POST uses to evaluate configurations. No processors results in a zero FOM. For board bringup, however, Sun Microsystems engineering sometimes wants POST to continue running even with no processors installed. This command tells POST to pretend that there is one processor in calculating the FOM if, actually, there are none. When no processors are present, POST can do only a very limited number of functions. But it can do a JTAG ASIC configuration, which is useful in certain bringup environments.

no_scard_probe (Level 2)

Do not probe for missing scards. scard is a generic term for an I/O adapter card, either SBus or PCI bus. If this command is invoked, all I/O card slots architecturally defined on the specific I/O module present are considered populated. This knowledge affects the Figure of Merit calculation done by POST, and is reported to OBP, allowing it to probe any slots declared populated by POST.

In the case of SBus cards, this probe-skipping also can be done by using the skip_test command for the appropriate probe test. However, there is no test for the probe in the case of a PCI I/O module; the probe is done by JTAG from the SSP.

no_scards_ok (Level 2)

Since the operating system cannot boot without I/O, the number of SBus cards (or, more generally, the number of populated I/O slots) is one component of the configuration Figure of Merit (FOM) used to evaluate configurations. No SBus cards result in a zero FOM. For board bringup, however, Sun Microsystems engineering sometimes wants POST to continue testing even with no SBus cards installed. This flag tells POST to pretend that one SBus card is present when it is calculating the FOM if, actually, there are none.

no_skip_phase_covers_npb (Level 2)

Where possible, POST tests the system resources in board loopback, using other onboard resources. This technique improves POST's ability to isolate failures and generally allows faster test execution, because more tests can run simultaneously on different system boards.

If a system board is not fully populated or has experienced onboard failures, POST must use offboard resources. For example, a board with no good processors (a nonprocessor board, or NPB) must use offboard processors to test its memory and I/O. A board with no good memory (a nonmemory Board, or NMB) must use offboard memory to run tests of processor and I/O versus memory. A board with a single processor must run crosscall interrupt tests against processors on other boards.

When a base test phase, such as onboard memory tests, has been skipped due to use of the skip_phase command, most technicians would assume that all the memory tests would be skipped. That assumption would lead to confusion if the NPB memory tests then take over and test the onboard memory later in POST. Therefore, the default behavior of POST is when such a base phase has been skipped, all phases that test the same resources offboard are also skipped automatically.

This is usually the desired behavior but, in some cases, it might not be. Forcing all tests to run out of loopback, while slower, can be an excellent stress test of the centerplane interconnect. Also, the technician or engineer might want to skip the base test, but run the NPB test while troubleshooting a particular problem. To support this, the no_skip_phase_covers_npb command suppresses the default implied skip of offboard phases when the base phase is skipped.

Note that while the command uses the abbreviation NPB, it actually affects all such offboard test phases, such as those for NMBs and xcall tests for single-processor boards.

Note also that the implied skip mechanism described operates only at the phase level. If all tests in a base phase have been skipped because of the skip_test command, the phase is not considered skipped.

no_snmp_access (Level 2)

Prevent POST from accessing the SSP's SNMP agent to obtain various information normally required for it to run. This command is provided to support various Sun Microsystems lab environments where the SNMP agent might not be running. It is effective only when used in a .postrc file in the current directory. The next component in the search path for .postrc requires the platform_name, which is obtained from the SNMP agent. If the .postrc file used is not in the local directory, POST ignores this command and generates a warning message.

Many of the items of information normally obtained from SNMP can be provided through the .postrc file, or through program defaults. See the following commands: interconnect_MHz, proc_freq_ratio, domain, logical_memboard_swap, platform_name, and no_snmp_freq_read.

no_snmp_invalidate_bootproc (Level 2)

By default, when a successful invocation of POST returns a boot processor number in the range [0,63], POST invalidates the SNMP value of the bootproc for the domain in which it is running before it starts interaction with the host. (Exception: POST does not invalidate the SNMP value when run in the special -H dynamic reconfiguration mode.) By invalidating this value, POST causes other SSP monitoring software, particularly the event detector daemon (EDD), to stop checking for arbstops and other events in this domain, possibly interfering with this hpost(1M) run.

The no_snmp_invalidate_bootproc command suppresses this invalidation. no_snmp_invalidate_bootproc is implied by no_snmp_access.

Note that POST never sets this SNMP element to a valid value, it only invalidates it. Setting it to a valid bootproc value is normally done by bringup(1M). Therefore, when POST is run other than by bringup(1M), the SNMP bootproc MIB element is invalidated and left that way.

no_snmp_memmap (Level 2)

Prevent POST from accessing the SSP's SNMP agent to obtain or modify the physical-to-logical memory board mapping. This prevention is implied if no_snmp_access is invoked. See the command logical_memboard_swap for more information about this mapping.

This command is effective only when used in a .postrc file in the current directory. If the .postrc file used is not in the local directory, this command is ignored and a warning message is generated.

no_snmp_freq_read (Level 2)

Prevent POST from accessing the SSP's SNMP agent to obtain the platform interconnect and processor frequency values. This prevention is implied if no_snmp_access is invoked. When either no_snmp_freq_read or no_snmp_access is used, POST takes these values from the .postrc commands interconnect_MHz and proc_freq_ratio, or from built-in default values.

no_stop_analyze (Level 2)

POST's normal action when detecting an arbstop or recordstop condition while running most tests is to read and analyze the status in the various ASICs, and to fail components when the fault can be determined. This command suppresses this function.

pc_color_freq code (Level 3)

The PC ASIC has a two-bit configuration parameter that controls the frequency with which PC changes the value of arbitration color, a property of the arbitration fairness algorithm. A default value is normally used. This command allows Sun Microsystems engineering to experiment with this parameter. This field is bits [19:18] of the configuration register.

pc_errmask {0|1 | io0|io1} bit_number (Level 3)

Allow individual bits in the error mask registers of PC ASICs to be forced to 0 during configuration, disabling the specified error from causing an arbstop. Multiple instances and versions of this command can be present; the bits to be masked are accumulated. If a number (0 or 1) follows this command, it affects only processor PCs; if the io form (io0 or io1) is used, it affects only I/O PCs. The 0 or 1 indicates which error mask register is specified. bit_number is an integer in the range 0-31, inclusive.

pc_grant_to 6-bit pse/value (Level 2)

Override normal PC ASIC configuration of this field, which is the Timeout/Hold config register bits [10:6].

pc_grant_to_io 6-bit_pse/value (Level 2)

Override normal PC ASIC configuration of this field, which is the Timeout/Hold config register bits [10:6] for I/O PCs. This command overrides any pc_grant_to command.

pc_loopback_always (Level 3)

Force PC loopback mode every time any PC is configured.

pc_loopback_lbus_enbl (Level 3)

During the initial processor module tests, POST uses a facility of the PC ASIC called PC loopback mode. In this mode, the PC does not send transactions through the CICs, but instead loops them back internally. This process allows better fault isolation, as you know that any failures in these tests are not related to the CICs or the PC-CIC signals.

As with board loopback, the PC has separate controls for PC loopback and driver enables for the local bus to the CIC. POST normally configures this so the drivers are disabled in PC loopback mode. This command causes these drivers to be enabled in PC loopback mode, so that they can be probed during debug. Compare this command to force_enbl_cp_driver.

pc_master_pio_req_limit 2-bit_code (Level 3)

Override normal PC ASIC configuration of this field for processor PCs. (It is always 0 for I/O PCs.) This is the Timeout/Hold config register bits [24:23].

pc_master_read_to 6-bit_pse/value (Level 2)

Override normal PC ASIC configuration of this field, which is the Timeout/Hold config register bits [5:0]. Bit [5], the most significant bit of this field, is the prescale enable for all of the master read, interrupt, and slave response timeouts in the PC.

pc_master_read_to_io 6-bit_pse/value (Level 2)

Override normal PC ASIC configuration of this field for I/O PCs. This field is the Timeout/Hold config register bits [5:0]. pc_master_read_to_io overrides any pc_master_read_to command.

pc_pc_hold 5-bit_value (Level 3)

Override normal PC ASIC configuration of this field. This field is the Timeout/Hold config register bits [22:18].

pc_slave_response_to 5-bit value (Level 2)

Override normal PC ASIC configuration of this field, using the specified 25-bit value for the Timeout/Hold config register bits [31:27]. Note that this timer uses the prescale enable for the master read timeout; see pc_master_read_to.

pc_slave_response_to_io 5-bit value (Level 2)

Override normal PC ASIC configuration of this field for I/O PCs, using the specified 5-bit value for the Timeout/Hold config register bits [31:27]. This command overrides any pc_slave_response_to command.

pc_slave_wr_to 6-bit_pse/value (Level 2)

Override normal PC ASIC configuration of this field. This field is the Timeout/Hold config register bits [16:12].

pc_slave_wr_to_io 6-bit_pse/value (Level 2)

Override normal PC ASIC configuration of this field for I/O PCs. This field is the Timeout/Hold config register bits [16:12]. pc_slave_wr_to_io overrides any pc_slave_wr_to command.

pc2_iopc_cic_perr_disable (Level 2)

Cause POST to disable I/O PC ASICs from detecting parity errors on the CIC control buses. This is required for operation if any boards in the system have the "magic wire" ECO. This is generally true for all boards that have a PC below Rev 4 in the I/O position (PC 2 on that board), since such PCs do not work reliably without this ECO.

phase_time_report (Level 2)

Report the elapsed time for each POST phase.

platform_name string (Level 2)

See command no_snmp_access. If that command is invoked, this command can provide the platform name, normally obtained from the SNMP agent. If no_snmp_access is not invoked, POST ignores this command. If no_snmp_access is invoked and this command is not present, POST uses $SUNW_HOSTNAME as the platform name.

This command is effective only when used in a .postrc file in the current directory. If the .postrc file used is not in the local directory, POST ignores this command and generates a warning message.

poll_timeout_mult mult_factor (Level 2)

The timeout values used when tasks are assigned to host processors are multiplied by this integer value, which is in the range 1 to 100, inclusive. Sometimes, when very verbose messages have been enabled in a system with many processors, a healthy processor is so delayed by the poll and display overhead that it exceeds the normal time allowed, causing it to be marked as failed. This command effectively extends all such timeout allowances. It can also be used as a field workaround for inappropriately short timeout values. See also servmgr_time_report and no_poll_timeouts.

port_idle_use_pause (Level 3)

Use the less flexible PORT_PAUSE PC BootBus feature instead of the PORT_IDLE feature.

print_all_errors (Level 2)

POST normally prints only the first message or two from any particular test; the test then quits. This command causes it to print all error messages and to continue testing.

Turning this function on can cause so many failure messages that the test timeout is exceeded, and a perfectly good processor can be marked as failed. To compensate, use the poll_timeout_mult command, as well.

proc_freq_check_percent {float_% | off} (Level 2)

During the JTAG integrity test phase, POST reads the maximum rated speed of each processor, and compares it to the speed of the system-wide processor clock distributed from the control board. If the clock speed exceeds the rated speed by greater than the specified percent (float_%), POST fails the processor. The default is 0.5%. If the argument is off, POST does not do the check.

proc_freq_ratio {2 | 2:1 | 3 | 3:1 | 3:2} (Level 2)

Use the specified ratio of processor frequency to system interconnect frequency. This value is used for reporting processor frequency in the post2obp structure, and for checking against a processor's rated maximum speed, in teststand environments lacking a real control board which can measure and report this frequency.

In systems that do have a control board, specifying this value causes POST to require that the measured ratio be within 0.5 percent of this value. If it is not specified, the measured ratio must be within 0.5 percent of the target ratio read from the SNMP server. See also the command interconnect_MHz.

proc_runslow_warn_percent[float_%|off] (Level 2)

POST normally checks the processor module's rated speed against the frequency provided by the control board to make sure processors are not being operated faster than rated. See proc_freq_check_percent. It also checks that processors are not running significantly slower than rated, which often means that the control board was misconfigured. If the speed is much slower than rated, POST displays a NOTE about the possible misconfiguration.

The NOTE is printed only if the control board processor frequency is proc_runslow_warn_percent below the rated module frequency. The default value is 9%. This command allows it to be set to a different value, or have the check and NOTE disabled completely.

proc_timestamp interval_secs (Level 2)

When printing messages from the downloaded processor code of all host processors (those messages preceded by {board.module}), also print a timestamp of when the messages occurred; but print timestamps for any particular processor only when that processor prints a message and at least interval_secs has elapsed since the last timestamp for that processor. The form of the timestamp is {board.module} {day/date/time}, with 1-second resolution.

interval_secs is an integer for the number of seconds in the range of 0 to 86400 (24 hours; 60 times 60 times 24). Specifying 0 causes every message to get a timestamp.

qt_missrefresh_err_enbl (Level 3)

See the quickturn command. POST's default behavior with quickturn specified is to mask missed refresh errors in the MC ASIC. qt_missrefresh_err_enbl causes these refresh errors to be enabled to cause an arbstop. POST quietly ignores this command if the quickturn command is not invoked.

quickturn KHz Mem_refresh_interval (Level 3)

Declare that the system is running in a Quickturn emulation environment. KHz declares the system clock speed, and must be in the range 100 to 2000 (2 MHz), inclusive. Mem_refresh_interval is the refresh interval in system clock cycles for configuring the MC, and must be in the range 8 to 0xFFF = 4095. Both arguments must be specified.

Poll timeouts are set at a multiple of their normal value, based on the declared system frequency. The memory controller is set to use the specified refresh interval. Other configuration properties might be changed appropriately when this command is invoked.

recordstop_poll (Level 2)

When polling for arbstop, also poll for recordstop.

redlist_file {filepath | none} (Level 2)

Command Line Equivalent: -R Use the values in the specified redlist(4) file rather than those in the default redlist(4) file, $SSPVAR/etc/platform_name/redlist. If none is specified, POST reads no redlist file. See blacklist(4) and redlist(4).

Be careful when using redlist_file on a production system; other SSP software does not know when POST is using a nonstandard redlist(4) file.

scantool_simulate (Level 3)

Intercept normal calls to the JTAG library functions and (crudely) simulate them internal to POST. This command is useful to Sun Microsystems engineering during development to allow code debug when no real or hardware simulated system is present.

servmgr_time_report (Level 2)

When a host processor is assigned a task, such as running a test, POST's server manager sets a timeout by which it must complete or be considered failed. This flag causes the server manager to report how much time remained in the timeout when the processor reported back. This information is useful in determining the appropriate value of these timeouts.

shared_mem brd boardmask (Level 3)

Configure the specified system board to provide shared memory to the system boards in boardmask. boardmask must not include any boards in the specified board's domain, including itself. See the domain command for more information. This command does not configure the shared memory BAR/LAR in the CICs; host software normally does so. However, see the command shmem_barlar.

shmem_barlar bar lar (Level 3)

Configure the JTAG CIC shared memory base and limit address registers with the given bar and lar values. This command affects POST only for boards declared by the shared_mem command to have shared memory, and only a single set of bar/lar values is used for all such boards. The default, and the value for boards without shared memory, is 1 for bar and 0 for lar (no valid range). For boards with shared memory, these two values are added to the board's base physical address (mod 2**41) and the result is that board's bar/lar configuration. These two registers count increments of 64 Kbytes, with implied [15:0] = 0. Any 25-bit value is acceptable for both bar and lar, and bar can be greater than lar.

skip_phase phase_name (Level 2)

Skip the named POST phase. Only one phase can be specified per command, but any number of skip_phase commands can appear in .postrc. To print the available phase names, execute hpost -?postrc. These names are also printed as progress messages when POST runs if the verbose level is sufficiently high. See also the interactive_use_postrc_skips and no_skip_phase_covers_npb commands.

skip_test test_id (Level 2)

Skip the designated test. Only one test can be specified per command, but any number of skip_test commands can appear in .postrc. test_id is a number in the range 0 to 0x1FF, used as index and identifier for a POST test. The test ID is printed, along with the test name, before each test is run, if the verbose level is high enough. Getting the test ID in this way is the most appropriate method for users to determine the ID they should use with this command. The test ID is also printed when tests fail.

This command provides higher resolution control over execution than skip_phase. It might also be a field workaround for bugs or hardware changes that cause inappropriate failures of some test.

Some POST tests can be internally declared nonskippable. A check for such declarations occurs at test execution time, rather than when POST reads the .postrc command. If a skip_test command is present for such a test, POST prints a single message that it is ignoring the command. See also the interactive_use_postrc_skips command.

sysreset_ignore_redlist (Level 3)

Allow redlisting of some system resources that physically do not exist, without causing POST to skip issuing the system reset during the init_reset phase. This command is for use only in certain development environments. See redlist(4).

system_red_any_fail (Level 2)

Upon any POST failure, immediately fail and internally redlist the entire host system. This command is sometimes useful for doing postmortem analysis of failures in a debugging environment.

Since it obviously subverts any possibility of POST managing to configure around failed components, Sun Microsystems does not intend this command for normal use. You can think of it as a more extreme form of the command board_red_any_fail.

trace_print board proc_module (Level 2)

Enable the extremely verbose tprintf trace prints from the specified host processor. This command is off by default. To control trace prints for multiple processors, use more than one instance of this command.

verbose level (Level 1)

Command Line Equivalent: -v Control the amount of progress information printed by POST. Higher verbose levels result in more verbose output. level is an integer from 0 to 255, inclusive. For more information about levels, execute hpost -?verbose.

The system administrator can use this command, but must be aware that high verbose levels slow POST execution. In some extreme cases, it slows it enough to cause timeouts.

verbose_print board proc_module (Level 2)

Control the verbose vprintf printing from an individual host processor. This command turns on control for one specific processor. To do so for multiple processors, use multiple instances of this command. This command is enabled for all processors if the verbose level is high enough.

SEE ALSO

bringup(1M), hpost(1M), blacklist(4), redlist(4).

SSP 3.5  Last Revised 31 Mar 2000

NAME | CAUTION | DESCRIPTION | PROPERTIES | SEE ALSO