Floating-Point Opcode Errors

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Caution -

The IA-32 Assembler generates the wrong object code for some of the floating-point opcodes fsub, fsubr, fdiv, and fdivr when there are two floating register operands, and the second op destination is not the zeroth floating-point register. This error has been made in many IA-32 assemblers and would probably cause problems if it were fixed.

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Replace the following instructions, in column 1, with their substitutions, in column 2, for IA-32 platforms:

Table 2-11 Floating-point Opcodes

fsub %st,%st(n)	fsubr %st, %st(n)
fsubp %st,%st(n)	fsubrp %st, %st(n)
fsub	fsubr
fsubr %st,%st(n)	fsub %st, %st(n)
fsubrp %st,%st(n)	fsubp %st, %st(n)
fsubr	fsub
fdiv %st,%st(n)	fdivr %st,%st(n)
fdivp %st,%st(n)	fdivrp %st,%st(n)
fdiv	fdivr
fdivr %st, %st(n)	fdvir %st, %st(n)
fdivrp %st, %st(n)	fdivp %st, %st(n)
fdivr	fdiv