SunVTS 6.0 Patch Set 2 Documentation Supplement for SPARC Platforms Table Of ContentsPrevious ChapterNext ChapterNoIndex


C H A P T E R  11
Level 3 Cache Test (l3sramtest)

l3sramtest exercises the level3 cache in the CPU module of Sun's Ultra-SPARC-IV+ systems. This is an external cache, with on-chip tags.

l3sramtest runs various subtests on the cache that try to exercise the cache by causing hits/misses, performing marching patterns on the level3 cache cells and writing patterns that cause electrical stress. This test also supports Cache Interconnect Stress test using SSO patterns that targets various interconnects between level 1, level 2 and level 3 caches.

l3sramtest is self scaling and adaptive. It scales with the size of the system. It will automatically retrieve the number of CPUs in the system and internally create that many threads to give coverage to the whole system at a given time. This test also dynamically determines the size and organization of the l3cache. The user does not have to input these values.

l3sramtest Options

To reach the following dialog box, right-click on the test name in the System Map and select Test Parameter Options. If you do not see this test in the System Map, you might need to expand the collapsed groups, or your system may not include the device appropriate to this test. Refer to the SunVTS User's Guide for more details.


FIGURE 11-1 l3sramtest Test Parameter Options Dialog Box





TABLE 11-1 l3sramtest Options

Option

Description

Thrash Cycles

Specifies the number of thrashing cycles the test completes for the level3 cache on the system. The default value is 32.

ECC Error Monitor

Enables or disables the ECC Error Monitor. The error monitor monitors the /var/adm/messagesfile for failure messages that could be caused due to the test. The default value is disabled--do not enable this option.

ECC Threshold

Specifies the threshold value of the number of errors after which the test would register an error. This argument is only applicable if the Error Monitor option is enabled. The errors that come on the /var/adm/messagescould be correctable, that is why the threshold value is provided to give a facility to ignore the errors if they are below the threshold value. The default value is 1.

Core Sync

Enables or disables the core syncronization mode. When this option is enabled, each CPU core runs with exclusive access to the cache during the entire cache test execution. The default value is disabled.

SSO

Enables or disables the Internal Cache Interconnect test. The default value is disabled.



Note - The l3sramtest automatically handles processor binding. Do not use the Processor Affinity option for the l3sramtest.


l3sramtest Test Modes


TABLE 11-2 l3sramtest Supported Test Modes

Test Mode

Description

Exclusive

Performs only the l3sramtest (full test).


l3sramtest Command-Line Syntax

/opt/SUNWvts/bin/sparcv9/l3sramtest [-standard_arguments] [-o

[dev=l3sram][,count=1..1024][,em=Enabled|Disabled][,threshold=0..255][,coresync=Enabled|Disabled][,corethreads=1..4][,sso=Enabled|Disabled]]


Note - The l3sramtest is not a per CPU test. There will be only one l3sramtest for the whole system (one image of Solaris). l3sramtest runs on all the CPUs of the domain.



TABLE 11-3 l3sramtest Command-Line Syntax

Argument

Description

dev=l3sram

Specifies the device. The default value is l3sram.

count=number

Specifies the number of thrashing cycles that the test completes for the level3 cache on the system. Default value for offline mode is 8.

em=Enabled/Disabled

Specifies the enabling or disabling of the ECC Error Monitor. The default value is disabled.

threshold=number

Specifies the threshold value of how many correctable ECC errors can occur in the elapsed time before l3sramtest reports a test failure. The default value is 1.

coresync=[Enabled/Disabled]

Specifies the enabling or disabling of the core syncronization mode. When this option is enabled, each CPU core runs with exclusive access to the cache during the entire cache test execution. The default value is disabled.

corethreads=number

Specifies the number of threads spawned per core. This is applicable in coresync and sso options only. The default value is 2.

sso=[Enabled/Disabled]

Specifies the enabling or disabling of the internal cache interconnect test. The default value is disabled.




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