Event Logs and POST Codes
|
This appendix contains information about the BIOS event log, the BMC system event log, the power-on self-test (POST), and console redirection. It contains the following sections:
Viewing Event Logs
Use this procedure to view the BIOS event log and the BMC system event log.
1. To turn on main power mode (all components powered on) if necessary, use a ball point pen or other stylus to press and release the Power button on the server front panel. See FIGURE 1-1.
When main power is applied to the full server, the Power/OK LED next to the Power button lights and remains lit.
2. Enter the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).
The BIOS Main menu screen is displayed.
3. View the BIOS event log.
a. From the BIOS Main Menu screen, select Advanced.
The Advanced Settings screen is displayed:
Main Advanced PCIPnP Boot Security Chipset Exit
******************************************************************************
* Advanced Settings * Configure CPU. *
* *************************************************** * *
* WARNING: Setting wrong values in below sections * *
* may cause system to malfunction. * *
* * *
* * CPU Configuration * *
* * IDE Configuration * *
* * Hyper Transport Configuration * *
* * ACPI Configuration * *
* * Event Log Configuration * *
* * IPMI 2.0 Configuration * *
* * MPS Configuration * *
* * PCI Express Configuration * * Select Screen *
* * Remote Access Configuration * ** Select Item *
* * USB Configuration * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
******************************************************************************
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
|
b. From the Advanced Settings screen, select Event Log Configuration.
The Advanced Menu Event Logging Details screen is displayed.
Advanced
******************************************************************************
* Event Logging details * View all unread events *
* *************************************************** * on the Event Log. *
* View Event Log * *
* Mark all events as read * *
* Clear Event Log * *
* * *
* * *
* * *
* * *
* * *
* * *
* * *
* * * Select Screen *
* * ** Select Item *
* * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
******************************************************************************
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
|
c. From the Event Logging Details screen, select View Event Log.
All unread events are displayed.
4. View the BMC system event log:
a. From the BIOS Main Menu screen, select Advanced.
The Advanced Settings screen is displayed.
b. From the Advanced Settings screen, select IPMI 2.0 Configuration.
The Advanced Menu IPMI 2.0 Configuration screen is displayed:
Advanced
******************************************************************************
* IPMI 2.0 Configuration * View all events in the *
* *************************************************** * BMC Event Log. *
* Status Of BMC Working * *
* * View BMC System Event Log * It will take up to *
* Reload BMC System Event Log * 60 Seconds approx. *
* Clear BMC System Event Log * to read all *
* * LAN Configuration * BMC SEL records. *
* * PEF Configuration * *
* BMC Watch Dog Timer Action [Disabled] * *
* * *
* * *
* * *
* * * Select Screen *
* * ** Select Item *
* * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
******************************************************************************
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
|
c. From the IPMI 2.0 Configuration screen, select View BMC System Event Log.
The log takes about 60 seconds to generate, then it is displayed on the screen.
5. If the problem with the server is not evident, continue with Using the ILOM Service Processor GUI to View System Information, or Viewing ILOM SP Event Logs.
Power-On Self-Test (POST)
The system BIOS provides a rudimentary power-on self-test. The basic devices required for the server to operate are checked, memory is tested, the LSI 1064 disk controller and attached disks are probed and enumerated, and the two Intel dual Gigabit Ethernet controllers are initialized.
The progress of the self-test is indicated by a series of POST codes. These codes are displayed at the bottom right corner of the system’s VGA screen (once the self-test has progressed far enough to initialize the system video). However, the codes are displayed as the self-test runs and scroll off of the screen too quickly to be read. An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Redirecting Console Output).
This section covers the following topics:
How BIOS POST Memory Testing Works
The BIOS POST memory testing is performed as follows:
1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is shadowed (that is, copied from ROM to DRAM).
2. Once executing out of DRAM, the BIOS performs a simple memory test (a write/read of every location with the pattern 55aa55aa).
| Note - Enabling Quick Boot causes the BIOS to skip the memory test. See Changing POST Options for more information.
|
| Note - Because the server can contain up to 64 MB of memory (128 MB for the X4440), the memory test can take several minutes. You can cancel POST testing by pressing any key during POST.
|
3. The BIOS polls the memory controllers for both correctable and uncorrectable memory errors and logs those errors into the service processor.
Redirecting Console Output
Use the following instructions to access the service processor and redirect the console output so that the BIOS POST codes can be read.
1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).
The BIOS Main menu screen is displayed.
2. Select the Advanced menu tab.
The Advanced Settings screen is displayed.
3. Select IPMI 2.0 Configuration.
The IPMI 2.0 Configuration screen is displayed.
4. Select the LAN Configuration menu item.
The LAN Configuration screen displays the service processor’s IP address.
5. To configure the service processor’s IP address (optional):
a. Select the IP Assignment option that you want to use (DHCP or Static).
- If you choose DHCP, the server’s IP address is retrieved from your network’s DHCP server and displayed using the following format:
Current IP address in BMC : xxx.xxx.xxx.xxx
- If you choose Static to assign the IP address manually, perform the following steps:
i. Type the IP address in the IP Address field.
You can also enter the subnet mask and default gateway settings in their respective fields.
ii. Select Commit and press Return to commit the changes.
iii. Select Refresh and press Return to see your new settings displayed in the Current IP address in BMC field.
6. Start a web browser and type the service processor’s IP address in the browser’s URL field.
7. When you are prompted for a user name and password, type the following:
- User Name: root
- Password: changeme
The Sun Integrated Lights Out Manager main GUI screen is displayed.
8. Click the Remote Control tab.
9. Click the Redirection tab.
10. Set the color depth for the redirection console at either 6 or 8 bits.
11. Click the Start Redirection button.
12. When you are prompted for a user name and password, type the following:
- User Name: root
- Password: changeme
The current POST screen is displayed.
Changing POST Options
These instructions are optional, but you can use them to change the operations that the server performs during POST testing. To change POST options:
1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).
The BIOS Main menu screen is displayed.
2. Select Boot.
The Boot Settings screen is displayed.
Main Advanced PCIPnP Boot Security Chipset Exit
*******************************************************************************
* Boot Settings * Configure Settings *
* *************************************************** * during System Boot. *
* * Boot Settings Configuration * *
* * *
* * Boot Device Priority * *
* * Hard Disk Drives * *
* * CD/DVD Drives * *
* * *
* * *
* * * Select Screen *
* * ** Select Item *
* * Enter Go to Sub Screen *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
*******************************************************************************
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
|
3. Select Boot Settings Configuration.
The Boot Settings Configuration screen is displayed.
Boot
*******************************************************************************
* Boot Settings Configuration * Allows BIOS to skip *
* *************************************************** * certain tests while *
* Quick Boot [Disabled] * booting. This will *
* Quiet Boot [Disabled] * decrease the time *
* AddOn ROM Display Mode [Force BIOS] * needed to boot the *
* Bootup Num-Lock [On] * system. *
* Wait For 'F1' If Error [Disabled] * *
* Interrupt 19 Capture [Enabled] * *
* * *
* * *
* * *
* * *
* * * Select Screen *
* * ** Select Item *
* * +- Change Option *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
*******************************************************************************
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
|
4. On the Boot Settings Configuration screen, there are several options that you can enable or disable:
- Quick Boot - This option is disabled by default. If you enable this, the BIOS skips certain tests while booting, such as the extensive memory test. This decreases the time it takes for the system to boot.
- Quiet Boot - This option is disabled by default. If you enable this, the Sun Microsystems logo is displayed instead of POST codes.
- Add On ROM Display Mode - This option is set to Force BIOS by default. This option has effect only if you have also enabled the Quiet Boot option, but it controls whether output from the Option ROM is displayed. The two settings for this option are as follows:
- Force BIOS - Remove the Sun logo and display Option ROM output.
- Keep Current - Do not remove the Sun logo. The Option ROM output is not displayed.
- Boot Num-Lock - This option is On by default (keyboard Num-Lock is turned on during boot). If you set this to off, the keyboard Num-Lock is not turned on during boot.
- Wait for F1 if Error - This option is disabled by default. If you enable this, the system will pause if an error is found during POST and will only resume when you press the F1 key.
- Interrupt 19 Capture - This option is reserved for future use. Do not change.
- Default Boot Order - The letters in the brackets represent the boot devices. To see the letters defined, position your cursor over the field and read the definition in the right side of the screen.
POST Codes
TABLE A-1 contains descriptions of each of the POST codes, listed in the same order in which they are generated. These POST codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST codes listed in TABLE A-1, the first two digits are from port 81 and the last two digits are from port 80.
TABLE A-1 POST Codes
|
POST Code
|
Description
|
|
00d0
|
Coming out of Power-On Reset (POR), PCI configuration space initialization.
|
|
00d2
|
Disable cache, full memory sizing, and verify that flat mode is enabled.
|
|
00d3
|
Memory detections and sizing in boot block, cache disabled, IO APIC enabled.
|
|
01d4
|
Test base 512KB memory. Adjust policies and cache first 8MB.
|
|
01d5
|
Bootblock code is copied from ROM to lower RAM. BIOS is now executing out of RAM.
|
|
01d6
|
Key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.
|
|
01d7
|
Restoring CPUID; moving bootblock-runtime interface module to RAM; determine whether to execute serial flash.
|
|
01d8
|
Uncompressing runtime module into RAM. Storing CPUID information in memory.
|
|
01d9
|
Copying main BIOS into memory.
|
|
01da
|
Giving control to BIOS POST.
|
|
0004
|
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default values.
|
|
00c2
|
Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
|
|
00c3
|
Errata workarounds applied to the BSP (#78 & #110).
|
|
00c6
|
Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate.
|
|
00c7
|
HT sets link frequencies and widths to their final values.
|
|
000a
|
Initializing the 8042 compatible Keyboard Controller.
|
|
000c
|
Detecting the presence of Keyboard in KBC port.
|
|
000e
|
Testing and initialization of different Input Devices. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
|
|
8600
|
Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
|
|
de00
|
Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
|
|
8613
|
Initialize PM regs and PM PCI regs at Early-POST. Initialize multi-host bridge, if system supports it. Setup ECC options before memory clearing.
|
|
0024
|
Uncompress and initialize any platform specific BIOS modules.
|
|
862a
|
BBS ROM initialization.
|
|
002a
|
Generic Device Initialization Manager (DIM) - Disable all devices.
|
|
042a
|
ISA PnP devices - Disable all devices.
|
|
052a
|
PCI devices - Disable all devices.
|
|
122a
|
ISA devices - Static device initialization.
|
|
152a
|
PCI devices - Static device initialization.
|
|
252a
|
PCI devices - Output device initialization.
|
|
202c
|
Initializing different devices. Detecting and initializing the video adapter installed in the system that have optional ROMs.
|
|
002e
|
Initializing all the output devices.
|
|
0033
|
Initializing the silent boot module. Set the window for displaying text information.
|
|
0037
|
Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
|
|
4538
|
PCI devices - IPL device initialization.
|
|
5538
|
PCI devices - General device initialization.
|
|
8600
|
Preparing CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
|
POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process.
TABLE A-2 describes the type of checkpoints that might occur during the POST portion of the BIOS. The BIOS uses the MCP55/IO55 chipset information. These two-digit checkpoints are the output from primary I/O port 80.
TABLE A-2 POST Code Checkpoints
|
POST Code
|
Description
|
|
03
|
Disable NMI, Parity, video for EGA, and DMA controllers. At this point, only ROM accesses go to the GPNV. If BB size is 64K, turn on ROM Decode below FFFF0000h. It should allow USB to run in the E000 segment. The HT must program the NB specific initialization and OEM specific initialization, and can program if it need be at beginning of BIOS POST, similar to overriding the default values of kernel variables.
|
|
04
|
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initialize data variables that are based on CMOS setup questions. Initialize both the 8259-compatible PICs in the system.
|
|
05
|
Initialize the interrupt controlling hardware (generally PIC) and interrupt vector table.
|
|
06
|
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to “POSTINT1ChHandlerBlock.”
|
|
C0
|
Early CPU Init Start--Disable Cache--Init Local APIC.
|
|
C1
|
Set up boot strap processor information.
|
|
C2
|
Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
|
|
C3
|
Errata workarounds applied to the BSP (#78 & #110).
|
|
C5
|
Enumerate and set up application processors. This includes microcode loading and workarounds for errata (#78, #110, #106, #107, #69, #63).
|
|
C6
|
Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs are left in the CLI HLT state.
|
|
C7
|
The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming.
|
|
0A
|
Initializes the 8042 compatible Keyboard Controller.
|
|
0B
|
Detects the presence of PS/2 mouse.
|
|
0C
|
Detects the presence of Keyboard in KBC port.
|
|
0E
|
Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.
|
|
13
|
Initialize PM regs and PM PCI regs at Early-POST, Initialize multi-host bridge, if system will support it. Setup ECC options before memory clearing. REDIRECTION causes corrected data to written to RAM immediately. CHIPKILL provides 4 bit error det/corr of x4 type memory.
|
|
20
|
Relocate all the CPUs to a unique SMBASE address. The BSP will be set to have its entry point at A000:0. If less than 5 CPU sockets are present on a board, subsequent CPUs entry points will be separated by 8000h bytes. If more than 4 CPU sockets are present, entry points are separated by 200h bytes. CPU module will be responsible for the relocation of the CPU to correct address. NOTE: APs are left in the INIT state.
|
|
24
|
Uncompress and initialize any platform-specific BIOS modules.
|
|
30
|
Initialize System Management Interrupt.
|
|
2A
|
Initializes different devices through DIM.
|
|
2C
|
Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
|
|
2E
|
Initializes all the output devices.
|
|
31
|
Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
|
|
33
|
Initializes the silent boot module. Set the window for displaying text information.
|
|
37
|
Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
|
|
38
|
Initializes different devices through DIM.
|
|
39
|
Initializes DMAC-1 and DMAC-2.
|
|
3A
|
Initialize RTC date/time.
|
|
3B
|
Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
|
|
3C
|
By this point, RAM read/write test is completed, program memory holes or handle any adjustments needed in RAM size with respect to NB. Test if HT Module found an error in BootBlock and CPU compatibility for MP environment.
|
|
40
|
Detect different devices (parallel ports, serial ports, and coprocessor in CPU,... etc.) successfully installed in the system and update the BDA, EBDA,... etc.
|
|
50
|
Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if required.
|
|
52
|
Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.
|
|
60
|
Initializes NUM-LOCK status and programs the KBD typematic rate.
|
|
75
|
Initialize Int-13 and prepare for IPL detection.
|
|
78
|
Initializes IPL devices controlled by BIOS and option ROMs.
|
|
7A
|
Initializes remaining option ROMs.
|
|
7C
|
Generate and write contents of ESCD in NVRam.
|
|
84
|
Log errors encountered during POST.
|
|
85
|
Displays errors to the user and gets the user response for error.
|
|
87
|
Execute BIOS setup if needed/requested.
|
|
8C
|
After all device initialization is done, program any user selectable parameters relating to NB/SB, such as timing parameters, non-cacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node.
|
|
8D
|
Build ACPI tables (if ACPI is supported).
|
|
8E
|
Program the peripheral parameters. Enable/Disable NMI as selected.
|
|
90
|
Late POST initialization of system management interrupt.
|
|
A0
|
Check boot password if installed.
|
|
A1
|
Clean-up work needed before booting to OS.
|
|
A2
|
Takes care of runtime image preparation for different BIOS modules. Fills the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.
|
|
A4
|
Initialize runtime language module.
|
|
A7
|
Displays the system configuration screen if enabled. Initializes the CPUs before boot, which includes the programming of the MTRRs.
|
|
A8
|
Prepare CPU for OS boot including final MTRR values.
|
|
A9
|
Wait for user input at configuration display if needed.
|
|
AA
|
Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
|
|
AB
|
Prepare BBS for Int 19 boot.
|
|
AC
|
Any kind of Chipsets (NB/SB) specific programming needed during End- POST, just before giving control to runtime code booting to OS. Program the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming needed during End-POST. Copy OEM specific data from POST_DSEG to RUN_CSEG.
|
|
B1
|
Save system context for ACPI.
|
|
00
|
Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
|
|
61-70
|
OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may be different from one platform to the next.
|
POST Error Codes
TABLE A-1 contains descriptions of each of the POST error codes, listed in the same order in which they are generated. These POST error codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST error codes listed in TABLE A-1, the first two digits are from port 81 and the last two digits are from port 80.
The Response column describes the action taken by the system on encountering the corresponding error. The choices are:
- Warning or Not an Error - The message appears on the screen. An error record is logged to the system event log (SEL). The system continues booting with a degraded state. The user might want to replace the unit.
- Pause - The message appears on the screen, an error is logged to the SEL, and user input is required to continue. The user can take immediate corrective action or choose to continue booting.
- Halt - The message appears on the screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.
TABLE A-3 Error Messages and Responses
|
Error Code
|
Error Message
|
|
|
0000
|
Timer Error
|
Pause
|
|
0003
|
CMOS Battery Low
|
Pause
|
|
0004
|
CMOS Settings Wrong
|
Pause
|
|
0005
|
CMOS Checksum Bad
|
Pause
|
|
000B
|
CMOS memory size Wrong
|
Pause
|
|
000C
|
RAM R/W test failed
|
Pause
|
|
000E
|
A: Drive Error
|
Pause
|
|
000F
|
B: Drive Error
|
Pause
|
|
0012
|
CMOS Date/Time Not Set
|
Pause
|
|
0040
|
Refresh Timer Test Failed
|
Halt
|
|
0041
|
Display Memory Test Failed
|
Pause
|
|
0042
|
CMOS Display Type Wrong
|
Pause
|
|
0043
|
~<INS> Pressed
|
Pause
|
|
0044
|
DMA Controller Error
|
Halt
|
|
0045
|
DMA-1 Error
|
Halt
|
|
0046
|
DMA-2 Error
|
Halt
|
|
0047
|
Unknown BIOS error. Error code = 0047
|
Halt
|
|
0048
|
Password Check Failed
|
Halt
|
|
0049
|
Unknown BIOS error. Error code = 0049
|
Halt
|
|
004A
|
Unknown BIOS error. Error code = 004A
|
Pause
|
|
004B
|
Unknown BIOS error. Error code = 004B
|
Pause
|
|
004C
|
Keyboard/Interface Error
|
Continue to boot
|
|
005D
|
S.M.A.R.T. Command Failed
|
Continue to boot
|
|
005E
|
Password Check Failed
|
Pause
|
|
0101
|
Warning! This system board does not support the power requirements of the installed processor. The processor will be run at a reduced frequency, which will impact system performance.
|
Pause
|
|
0102
|
Error! The CPU Core to Bus ratio or VID configuration has failed! Please enter BIOS Setup and re-config it.
|
Pause
|
|
0103
|
ERROR! CPU MTRRs configuration failed!
Uncacheable memory hole or PCI space too complicated.
|
Continue to boot
|
|
0120
|
Thermal Trip Failure
|
Pause
|
|
0121
|
Thermal Trip Failure
|
Pause
|
|
0122
|
Thermal Trip Failure
|
Pause
|
|
0123
|
Thermal Trip Failure
|
Pause
|
|
0124
|
Thermal Trip Failure
|
Pause
|
|
0125
|
Thermal Trip Failure
|
Pause
|
|
0126
|
Thermal Trip Failure
|
Pause
|
|
0127
|
Thermal Trip Failure
|
Pause
|
|
0128
|
Thermal Trip Failure
|
Continue to boot
|
|
0129
|
Thermal Trip Failure
|
Continue to boot
|
|
012A
|
Thermal Trip Failure
|
Continue to boot
|
|
012B
|
Thermal Trip Failure
|
Continue to boot
|
|
012C
|
Thermal Trip Failure
|
Continue to boot
|
|
012D
|
Thermal Trip Failure
|
Continue to boot
|
|
012E
|
Thermal Trip Failure
|
Continue to boot
|
|
012F
|
Thermal Trip Failure
|
Continue to boot
|
|
0150
|
Processor Failed BIST
|
Pause
|
|
0151
|
Processor Failed BIST
|
Pause
|
|
0152
|
Processor Failed BIST
|
Pause
|
|
0153
|
Processor Failed BIST
|
Pause
|
|
0154
|
Processor Failed BIST
|
Pause
|
|
0155
|
Processor Failed BIST
|
Pause
|
|
0156
|
Processor Failed BIST
|
Pause
|
|
0157
|
Processor Failed BIST
|
Pause
|
|
0158
|
Processor Failed BIST
|
Continue to boot
|
|
0159
|
Processor Failed BIST
|
Continue to boot
|
|
015A
|
Processor Failed BIST
|
Continue to boot
|
|
015B
|
Processor Failed BIST
|
Continue to boot
|
|
015C
|
Processor Failed BIST
|
Continue to boot
|
|
015D
|
Processor Failed BIST
|
Continue to boot
|
|
015E
|
Processor Failed BIST
|
Continue to boot
|
|
015F
|
Processor Failed BIST
|
Continue to boot
|
|
0160
|
Processor missing microcode
|
Pause
|
|
0161
|
Processor missing microcode
|
Pause
|
|
0162
|
Processor missing microcode
|
Pause
|
|
0163
|
Processor missing microcode
|
Pause
|
|
0164
|
Processor missing microcode
|
Pause
|
|
0165
|
Processor missing microcode
|
Pause
|
|
0166
|
Processor missing microcode
|
Pause
|
|
0167
|
Processor missing microcode
|
Pause
|
|
0168
|
Processor missing microcode
|
Continue to boot
|
|
0169
|
Processor missing microcode
|
Continue to boot
|
|
016A
|
Processor missing microcode
|
Continue to boot
|
|
016B
|
Processor missing microcode
|
Continue to boot
|
|
016C
|
Processor missing microcode
|
Continue to boot
|
|
016D
|
Processor missing microcode
|
Continue to boot
|
|
016E
|
Processor missing microcode
|
Continue to boot
|
|
016F
|
Processor missing microcode
|
Continue to boot
|
|
0180
|
BIOS does not support current stepping
|
Pause
|
|
0181
|
BIOS does not support current stepping
|
Pause
|
|
0182
|
BIOS does not support current stepping
|
Pause
|
|
0183
|
BIOS does not support current stepping
|
Pause
|
|
0184
|
BIOS does not support current stepping
|
Pause
|
|
0185
|
BIOS does not support current stepping
|
Pause
|
|
0186
|
BIOS does not support current stepping
|
Pause
|
|
0187
|
BIOS does not support current stepping
|
Pause
|
|
0188
|
BIOS does not support current stepping
|
Continue to boot
|
|
0189
|
BIOS does not support current stepping
|
Continue to boot
|
|
018A
|
BIOS does not support current stepping
|
Continue to boot
|
|
018B
|
BIOS does not support current stepping
|
Continue to boot
|
|
018C
|
BIOS does not support current stepping
|
Continue to boot
|
|
018D
|
BIOS does not support current stepping
|
Continue to boot
|
|
018E
|
BIOS does not support current stepping
|
Continue to boot
|
|
018F
|
BIOS does not support current stepping
|
Continue to boot
|
|
0192
|
L2 cache size mismatch
|
Continue to boot
|
|
0193
|
CPUID, Processor stepping are different
|
Continue to boot
|
|
0194
|
CPUID, Processor family are different
|
Pause
|
|
0195
|
Front side bus mismatch. System halted.
|
Continue to boot
|
|
0196
|
CPUID, Processor Model are different.
|
Pause
|
|
0197
|
Processor speeds mismatched.
|
Pause
|
|
5120
|
CMOS cleared by jumper.
|
Pause
|
|
5121
|
Password cleared by jumper.
|
Pause
|
|
5125
|
Not enough conventional memory to copy PCI Option ROM
|
Continue to boot
|
|
5180
|
Unsupported Memory Vendor : DIMM_A0
|
Warning
|
|
5181
|
Unsupported Memory Vendor : DIMM_A1
|
Warning
|
|
5182
|
Unsupported Memory Vendor : DIMM_A2
|
Warning
|
|
5183
|
Unsupported Memory Vendor : DIMM_A3
|
Warning
|
|
5184
|
Unsupported Memory Vendor : DIMM_A4
|
Continue to boot
|
|
5185
|
Unsupported Memory Vendor : DIMM_B0
|
Warning
|
|
5186
|
Unsupported Memory Vendor : DIMM_B1
|
Warning
|
|
5187
|
Unsupported Memory Vendor : DIMM_B2
|
Warning
|
|
5188
|
Unsupported Memory Vendor : DIMM_B3
|
Warning
|
|
5189
|
Unsupported Memory Vendor : DIMM_B4
|
Warning
|
|
518A
|
Unsupported Memory Vendor : DIMM_B5
|
Warning
|
|
518B
|
Unsupported Memory Vendor : DIMM_C0
|
Warning
|
|
518C
|
Unsupported Memory Vendor : DIMM_C1
|
Warning
|
|
518D
|
Unsupported Memory Vendor : DIMM_C2
|
Warning
|
|
518F
|
Unsupported Memory Vendor : DIMM_C3
|
Warning
|
|
5190
|
Unsupported Memory Vendor : DIMM_C4
|
Warning
|
|
5191
|
Unsupported Memory Vendor : DIMM_C5
|
Warning
|
|
5192
|
Unsupported Memory Vendor : DIMM_D0
|
Warning
|
|
5193
|
Unsupported Memory Vendor : DIMM_D1
|
Warning
|
|
5194
|
Unsupported Memory Vendor : DIMM_D2
|
Warning
|
|
5195
|
Unsupported Memory Vendor : DIMM_D3
|
Warning
|
|
5196
|
Unsupported Memory Vendor : DIMM_D4
|
Warning
|
|
5197
|
Unsupported Memory Vendor : DIMM_D5
|
Warning
|
|
51A0
|
Unsupported AMB Vendor : DIMM_A0
|
Warning
|
|
51A1
|
Unsupported AMB Vendor : DIMM_A1
|
Warning
|
|
51A2
|
Unsupported AMB Vendor : DIMM_A2
|
Warning
|
|
51A3
|
Unsupported AMB Vendor : DIMM_A3
|
Warning
|
|
51A4
|
Unsupported AMB Vendor : DIMM_A4
|
Warning
|
|
51A5
|
Unsupported AMB Vendor : DIMM_A5
|
Warning
|
|
51A6
|
Unsupported AMB Vendor : DIMM_B0
|
Warning
|
|
51A7
|
Unsupported AMB Vendor : DIMM_B1
|
Warning
|
|
51A8
|
Unsupported AMB Vendor : DIMM_B2
|
Pause
|
|
51A9
|
Unsupported AMB Vendor : DIMM_B3
|
Warning
|
|
51AA
|
Unsupported AMB Vendor : DIMM_B4
|
Warning
|
|
51AB
|
Unsupported AMB Vendor : DIMM_B5
|
Warning
|
|
51AC
|
Unsupported AMB Vendor : DIMM_C0
|
Warning
|
|
51AD
|
Unsupported AMB Vendor : DIMM_C1
|
Pause
|
|
51AE
|
Unsupported AMB Vendor : DIMM_C2
|
Warning
|
|
51AF
|
Unsupported AMB Vendor : DIMM_C3
|
Pause
|
|
51B0
|
Unsupported AMB Vendor : DIMM_C4
|
Pause
|
|
51B1
|
Unsupported AMB Vendor : DIMM_C5
|
Pause
|
|
51B2
|
Unsupported AMB Vendor : DIMM_D0
|
Continue to boot
|
|
51B3
|
Unsupported AMB Vendor : DIMM_D1
|
Continue to boot
|
|
51B4
|
Unsupported AMB Vendor : DIMM_D2
|
Continue to boot
|
|
51B5
|
Unsupported AMB Vendor : DIMM_D3
|
Continue to boot
|
|
51B6
|
Unsupported AMB Vendor : DIMM_D4
|
Continue to boot
|
|
51B7
|
Unsupported AMB Vendor : DIMM_D5
|
Continue to boot
|
|
51C0
|
Memory Configuration Error.
|
Continue to boot
|
|
8101
|
Warning! USB Host Controller not found at the specified address!!!
|
Continue to boot
|
|
8102
|
Error! USB device failed to initialize!!!
|
Continue to boot
|
|
8104
|
Warning! Port 60h/64h emulation is not supported by this USB Host Controller!!!
|
Continue to boot
|
|
8105
|
Warning! EHCI controller disabled. It requires 64bit data support in the BIOS.
|
Continue to boot
|
|
8301
|
Not enough space in runtime area. SMBIOS data will not be available.
|
Continue to boot
|
|
8302
|
Not enough space in runtime area. SMBIOS data will not be available.
|
Continue to boot
|
|
8601
|
Error: BMC Not Responding
|
Continue to boot
|
|
8701
|
Insufficient Runtime space for MPS data.!!.
System may operate in PIC or Non-MPS mode.
|
Continue to boot
|
| Sun Fire X4140, X4240, and X4440 Servers Diagnostics Guide
|
820-3067-14
|
   
|
Copyright © 2010, Oracle and/or its affiliates. All rights reserved.